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march 2012 i ? 2012 microsemi corporation axcelerator family fpgas leading-edge performance ? 350+ mhz system performance ? 500+ mhz internal performance ? high-performance embedded fifos ? 700 mb/s lvds capable i/os specifications ? up to 2 million equivalent system gates ? up to 684 i/os ? up to 10,752 dedicated flip-flops ? up to 295 kbits embedded sram/fifo ? manufactured on advanced 0.15 m cmos antifuse process technology, 7 layers of metal features ? single-chip, nonvolatile solution ? up to 100% resource utilization with 100% pin locking ? 1.5 v core voltage for low power ? footprint compatible packaging ? flexible, multi-standard i/os: ? 1.5 v, 1.8 v, 2.5 v, 3.3 v mixed voltage operation ? bank-selectable i/os ? 8 banks per chip ? single-ended i/o standards: lvttl, lvcmos, 3.3v pci, and 3.3 v pci-x ? differential i/o sta ndards: lvpecl and lvds ? voltage-referenced i/o standards: gtl+, hstl class 1, sstl2 class 1 and 2, sstl3 class 1 and 2 ? registered i/os ? hot-swap compliant i/os (except pci) ? programmable slew rate and drive strength on outputs ? programmable delay and weak pull-up/pull-down circuits on inputs ? embedded memory: ? variable-aspect 4,608-bit ram blocks (x1, x2, x4, x9, x18, x36 organizations available) ? independent, width-configurable read and write ports ? programmable embedded fifo control logic ? segmentable clock resources ? embedded phase-locked loop: ? 14-200 mhz input range ? frequency synthesis capabilities up to 1 ghz ? deterministic, user-controllable timing ? unique in-system diagnostic and debug capability with microsemi silicon explorer ii ? boundary-scan testing compli ant with ieee standard 1149.1 (jtag) ? fuselock? programming technology protects against reverse engineering and design theft table 1 ? axcelerator family product profile device ax125 ax250 AX500 ax1000 ax2000 capacity (in equivalent system gate s) 125,000 250,000 500,000 1,000,000 2,000,000 typical gates 82,000 154,000 286,000 612,000 1,060,000 modules register (r-cells) 672 1,408 2,688 6,048 10,752 combinatorial (c-cells) 1,344 2,816 5,376 12,096 21,504 maximum flip-flops 1,344 2,816 5,376 12,096 21,504 embedded ram/fifo number of core ram blocks 4 12 16 36 64 total bits of core ram 18,432 55,296 73,728 165,888 294,912 clocks (segmentable) hardwired 4 4 4 4 4 routed 4 4 4 4 4 plls 88888 i/os i/o banks 8 8 8 8 8 maximum user i/os 168 248 336 516 684 maximum lvds channels 84 124 168 258 342 total i/o registers 504 744 1,008 1,548 2,052 package pq bg fg cq cg 256, 324 208 256, 484 208, 352 208 484, 676 208, 352 729 484, 676, 896 352 624 896, 1152 256, 352 624 revision 18
axcelerator family fpgas ii revision 18 ordering information device resources user i/os (including clock buffers) package ax125 ax250 AX500 ax1000 ax2000 pq208 ? 115 115 ? ? cq208 ? 115 115 ? ? cq256 ? ? ? ? 136 fg256 138 138 ? ? ? fg324 168???? cq352 ? 198 198 198 198 fg484 ? 248 317 317 ? cg624 ? ? ? 418 418 fg676 ? ? 336 418 ? bg729 ???516? fg896 ? ? ? 516 586 fg1152 ????684 note: the fg256, fg324, and fg484 are footprin t compatible with one another. the fg676, fg896, and fg1152 are also footprint compatible with one another. lead-free packaging blank = standard packaging g= rohs-compliant packaging ax1000 1 fg _ blank = standard speed = approximately 15% faster than standard 1 = approximately 25% faster than standard 2 package type = ball grid array (1.27mm pitch) = fine ball grid array (1.0mm pitch) pq = plastic quad flat pack (0.5mm pitch) cq = ceramic quad flat pack (0.5mm pitch) 896 i package lead count g application blank = commerc ial (0 to +70 c) i = industrial (-40 to +85 c) pp = pre-production 125,000 equivalent system gates ax125 = ax250 250,000 equivalent system gates = AX500 500,000 equivalent system gates = ax1000 1,000,000 equivalent system gates = ax2000 2,000,000 equivalent system gates = part number speed grade bg fg cg = ceramic column grid array m = military (-55 to +125 c)
axcelerator family fpgas revision 18 iii axcelerator family device status temperature grade offerings speed grade and temperature grade matrix axcelerator ? devices status ax125 production ax250 production AX500 production ax1000 production ax2000 production package ax125 ax250 AX500 ax1000 ax2000 pq208 ? c, i, m c, i, m ? ? cq208 ? m m ? ? cq256 ? ? ? ? m fg256 c, i c, i, m ? ? ? fg324 c, i ? ? ? ? cq352 ? m m m m fg484 ? c, i, m c, i, m c, i, m ? cg624 ? ? ? m m fg676 ? ? c, i, m c, i, m ? bg729 ? ? ? c, i, m ? fg896 ? ? ? c, i, m c, i, m fg1152 ? ? ? ? c, i, m c = commercial i = industrial m = military temperature grade std ?1 ?2 c 33 3 i 33 3 m 33 ? c = commercial i = industrial m = military
axcelerator family fpgas iv revision 18 packaging data refer to the following documents located on the microsemi so c products group website for additional packaging information. package mechanical drawings package thermal characteristics and weights hermatic package mechanical information contact your local microsemi representative for device availability.
axcelerator family fpgas revision 18 v table of contents general description device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 design environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 detailed specifications operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 i/o specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 voltage-referenced i/o standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43 differential standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54 routing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61 global resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66 axcelerator clock management system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-75 embedded memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-86 other architectural features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-106 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-110 package pin assignments bg729 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 fg256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 fg324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 fg484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 fg676 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 fg896 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52 fg1152 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71 pq208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-84 cq208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89 cq256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94 cq352 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-98 cg624 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-115 datasheet information list of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 datasheet categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 safety critical, life support, and high-reliability applications policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

revision 18 1-1 1 ? general description axcelerator devices offer high performance at densit ies of up to two million equivalent system gates. based upon the microsemi ax architecture, axcelera tor has several system-level features such as embedded sram (with comp lete fifo control logic), plls, se gmentable clocks, chip-wide highway routing, and carry logic. device architecture ax architecture, derived from the highly-succe ssful sx-a sea-of-modules architecture, has been designed for high performance and total logic module utilization ( figure 1-1 ). unlike in traditional fpgas, the entire floor of the axcelerator device is covere d with a grid of logic modules, with virtually no chip area lost to interconnect elements or routing. programmable inte rconnect element the axcelerator family uses a patented metal-to-metal antifuse programmable interconnect element that resides between the upper two layers of metal ( figure 1-2 on page 1-2 ). this completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on traditional fpgas) and enables the efficient sea-of-modules ar chitecture. the antifuses are normally open circuit and, when programmed, form a permanent, passive, low-impedance connection, leading to the fastest signal propagation in the industry. in addition, th e extremely small size of these interconnect elements gives the axcelerator family abundant routing resources. the very nature of microsemi's nonvolatile antifuse technology provides excellent protection against design pirating and cloning (fuselock technology). typical cloning attempts are impossible (even if the security fuse is left unprogrammed) as no bitstream or programming file is ever downloaded or stored in the device. reverse engineering is virtually impossib le due to the difficulty of trying to distinguish between programmed and unprogrammed antifuses and also due to the programming methodology of antifuse devices (see "security" on page 2-108 ). figure 1-1 ? sea-of-modules comparison switch matrix routing logic block logic modules sea-of-modules architecture traditional fpga architecture
general description 1-2 revision 18 logic modules microsemi's axcelerator family provides two types of logic modules: the register cell (r-cell) and the combinatorial cell (c-cell). the axcelerator device can implement more than 4,000 combinatorial functions of up to five inputs ( figure 1-3 ). the r-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and active-low enable control signals ( figure 1-3 ). the r-cell registers feature programmable clock polarity selectable on a register-by-register basis. this provides additional flexibility (e.g., easy mapping of dual-data-rate functions into the fpga) while conserving valuable cl ock resources. the clock source for the r-cell can be chosen from the hardwired clocks, routed clocks, or internal logic. figure 1-2 ? axcelerator family interconnect elements figure 1-3 ? ax c-cell and r-cell c-cell a[1:0] b[1:0] d[3:0] db cfn fco fci y pset clr d e clk q (positive edge triggered) c-cell r-cell
axcelerator family fpgas revision 18 1-3 two c-cells, a single r-cell, two transmit (tx), an d two receive (rx) routing buffers form a cluster, while two clusters comprise a supercluster ( figure 1-4 ). each supercluster also contains an independent buffer (b) module, which supports buffer insertion on high-fanout nets by the place-and- route tool, minimizing system dela ys while improving logic utilization. the logic modules within the supercluster are arrang ed so that two combinatorial modules are side-by- side, giving a c?c?r ? c?c?r pattern to the supercluster. this c?c?r pattern enables efficient implementation (minimum delay) of two-bit carry logic for improved arithmetic performance ( figure 1-5 on page 1-3 ). the ax architecture is fully fracturable, meaning that if one or more of the logic modules in a supercluster are used by a particul ar signal path, the other logic modules are still available for use by other paths. at the chip level, superclusters are organized into core tiles, which are arrayed to build up the full chip. for example, the ax1000 is composed of a 3x3 array of nine core tiles. surrounding the array of core tiles are blocks of i/o cluste rs and the i/o bank ring ( table 1-1 ). each core tile consis ts of an array of 336 superclusters and four sram blocks (176 super clusters and three sram blocks for the ax250). figure 1-4 ? ax supercluster figure 1-5 ? ax 2-bit carry logic table 1-1 ? number of core tiles per device device number of core tiles ax125 1 regular tile ax250 4 smaller tiles AX500 4 regular tiles ax1000 9 regular tiles ax2000 16 regular tiles rx tx b c r c c c r rx rx rx tx tx tx dcout y y c-cell c-cell carry logic fci fco
general description 1-4 revision 18 the sram blocks are arranged in a column on the west side of the tile ( figure 1-6 on page 1-4 ). embedded memory as mentioned earlier, each core tile has either thre e (in a smaller tile) or four (in the regular tile) embedded sram blocks along the west side, and each variable-aspect-ratio sram block is 4,608 bits in size. available memory configurations are: 128x36, 256x18, 512x9, 1kx4, 2kx2 or 4kx1 bits. the individual blocks have separate read and write ports that can be configured with different bit widths on each port. for example, data can be wr itten in by eight and read out by one. in addition, every sram block has an embedded fi fo control unit. the contro l unit allows the sram block to be configured as a synchronous fifo without using core logic modules. the fifo width and depth are programmable. the fifo also featur es programmable almost-empty (aempty) and almost-full (afull) flags in addition to the normal empty and full flags. in addition to the flag logic, the embedded fifo control unit also contains the counters necessary for the generation of the read and write address pointers as well as cont rol circuitry to prevent metastability and erroneous operation. the embedded sram/fifo blocks can be cascaded to create larger configurations. i/o logic the axcelerator family of fpgas features a flexible i/o structure, supporting a range of mixed voltages with its bank-selectable i/os: 1.5v, 1.8v, 2.5v, and 3. 3v. in all, axcelerator fpgas support at least 14 different i/o standards (single-ended, differential, voltage-referenced). the i/os are organized into banks, with eight banks per device (two per side). th e configuration of these banks determines the i/o standards supported (see "user i/os" on page 2-11 for more information). all i/o standards are available in each bank. each i/o module has an input register (inreg), an output register (outreg), and an enable register (enreg) ( figure 1-7 on page 1-5 ). an i/o cluster includes two i/o modules, four rx modules, two tx modules, and a buffer (b) module. figure 1-6 ? ax device architecture (ax1000 shown) chip layout supercluster i/o structure see figure 7 ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc ramc hd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc hd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc hd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc s c sc sc sc sc sc hd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc hd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc hd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc hd sc sc sc sc rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd rd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc hd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc hd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc hd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc hd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc hd sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc sc hd sc sc sc sc core tile 4k ram/ fifo 4k ram/ fifo 4k ram/ fifo 4k ram/ fifo rx tx b c r c c c r rx rx rx tx tx tx
axcelerator family fpgas revision 18 1-5 routing the ax hierarchical routing structure ties the lo gic modules, the embedded memory blocks, and the i/o modules together ( figure 1-8 on page 1-6 ). at the lowest level, in an d between superclusters, there are three local routing structures: fa stconnect, directconnect, and carry connect routing. directconnects provide the highest performance rout ing inside the superclusters by connecting a c-cell to the adjacent r-cell. directconnects do not require an antifuse to make the connection and achieve a signal propagation time of less than 0.1 ns. fastconnects provide high-performance, horizontal r outing inside the supercluster and vertical routing to the supercluster immediately below it. only on e programmable connection is used in a fastconnect path, delivering a maximum routing delay of 0.4 ns. carryconnects are used for routing carry logic betwe en adjacent superclusters. they connect the fco output of one two-bit, c-cell carry logic to the fc i input of the two-bit, c-cell carry logic of the supercluster below it. carryconnects do not require an antifuse to make the connection and achieve a signal propagation time of less than 0.1 ns. the next level contains the core tile routing. over the super clusters within a core tile, both vertical and horizontal tracks run across rows or columns, respecti vely. at the chip level, vertical and horizontal tracks extend across the full length of the device, both north- to-south and east-to-w est. these tracks are composed of highway routing that extend the en tire length of the device (segmented at core tile boundaries) as well as segmented routing of varying lengths. figure 1-7 ? i/o cluster arrangement i/o cluster i/o module coretile 4k ram/ fifo 4k ram/ fifo 4k ram/ fifo 4k ram/ fifo outreg enreg inreg i/o module i/o module rx rx rx rx tx tx b n i o b a k
general description 1-6 revision 18 global resources each family member has three types of global signals available to the designer: hclk, clk, and gclr/gpset. there are four hardwired clocks (hclk) per device that can directly drive the clock input of each r-cell. each of the four routed clocks (clk) can drive the clock, clear, preset, or enable pin of an r-cell or any input of a c-cell ( figure 1-3 on page 1-2 ). global clear (gclr) and global preset (gpset) drive the clear and preset inputs of each r-cell as well as each i/o register on a chip-wide basis at power-up. each hclk and clk has an associated analog pll (a total of eight per chip). each embedded pll can be used for clock delay minimization, clock delay adj ustment, or clock frequency synthesis. the pll is capable of operating with input frequencies rang ing from 14 mhz to 200 mhz and can generate output frequencies between 20 mhz and 1 ghz. the clock can be either divided or multiplied by factors ranging from 1 to 64. additionally, multiply and divide sett ings can be used in any combination as long as the resulting clock frequency is between 20 mhz and 1 ghz. adjacent plls can be cascaded to create complex frequency combinations. the pll can be used to introduce either a positive or a negative clock delay of up to 3.75 ns in 250 ps increments. the reference clock required to drive th e pll can be derived from three sources: external input pad (either single-ended or differential), in ternal logic, or the ou tput of an adjacent pll. low power (lp) mode the ax architecture was created for high-perfor mance designs but also includes a low power mode (activated via the lp pin). when the low power mode is activated, i/o banks can be disabled (inputs disabled, outputs tristated), and plls can be placed in a power-down mode. all internal register states are maintained in this mode. furthermore, individual i/o banks can be configured to opt out of the lp mode, thereby giving the designer access to critical si gnals while the rest of the chip is in low power mode. the power can be further reduced by providing an external voltage source (v pump ) to the device to bypass the internal charge pump (see "low power mode" on page 2-106 for more information). figure 1-8 ? ax routing structures
axcelerator family fpgas revision 18 1-7 design environment the axcelerator family of fpgas is fu lly supported by both microsemi's libero ? integrated design environment and designer fpga development software. libero ide is an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. additionally, libero ide allows users to integrate both schematic and hdl synthesis into a single flow and verify the entire design in a single environment (see the libero ide flow diagram located on the microsemi soc products group website). libero ide includes synplify ? actel edition (ae) from synplicity ? , viewdraw ? ae from mentor graphics ? , model sim ? hdl simulator from mentor graphics, waveformer lite? ae from synapticad ? , and designer software from microsemi. designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for fpga development. the designer software includes the following: ? timer ? a world-class integrated static ti ming analyzer and constraints editor which support timing-driven place-and-route ? netlistviewer ? a design netlist schematic viewer ? chipplanner ? a graphical floorplanner viewer and editor ? smartpower ? allows the designer to quickly estimate the power consumption of a design ? pineditor ? a graphical application for editing pin assignments and i/o attributes ? i/o attribute editor ? displays all assigned and unassigned i/o macros and their attributes in a spreadsheet format with the designer software, a user can lock the desi gn pins before layout while minimally impacting the results of place-and-route. additionally, microsemi?s back-annotation flow is compatible with all the major simulators and the simulation resu lts can be cross-probed with silicon explorer ii, microsemi?s integrated verification and logic analysis tool. another tool included in the designer software is the smartgen core generator, which easily cr eates popular and commonly used logic f unctions for implementation into your schematic or hdl design. designer software is compatible with the most pop ular fpga design entry and verification tools from eda vendors, such as mentor graphics, synplicit y, synopsys, and cadence design systems. the designer software is available for bo th the windows and unix operating systems. programming programming support is provided through silicon scul ptor ii, a single-site programmer driven via a pc- based gui. in addition, bp microsystems offers multi- site programmers that provide qualified support for microsemi devices. factory programming is available for high-volume production needs. in-system diagnostic and debug capabilities the axcelerator family of fpgas includes internal probe circuitry, allowing the designer to dynamically observe and analyze any signal inside the fpga without disturbing norma l device operation ( figure 1-9 ). figure 1-9 ? probe setup serial connection additional 14 channels (logic analyzer) axcelerator fpgas silicon explorer ii tdi tck tms 16 pin connection 22 pin connection pra prb tdo ch3/prc ch4/prd
general description 1-8 revision 18 up to four individual signals can be brought out to dedicated probe pins (pra/b/c/d) on the device. the probe circuitry is accessed and controlled via silicon explorer ii, microsemi's integrated verification and logic analysis tool that attaches to the serial port of a pc and communicates with the fpga via the jtag port (see "silicon explorer ii probe interface" on page 2-109 ). summary microsemi?s axcelerator family of fpgas extends the successful sx-a architecture, adding embedded ram/fifos, plls, and high-speed i/os. with the suppor t of a suite of robust software tools, design engineers can incorporate high gate counts and fixed pins into an axcelerator design yet still achieve high performance and efficient device utilization. related documents application notes simultaneous switching noise and signal integrity http://www.microsemi.com/s oc/documents/ssn_an.pdf axcelerator family pll and clock management http://www.microsemi.com/s oc/documents/ax_pll_an.pdf implementation of security in actel antifuse fpgas http://www.microsemi.com/soc/doc uments/antifuse_security_an.pdf user?s guides and manuals antifuse macro library guide http://www.microsemi.com/s oc/documents/libguide_ug.pdf smartgen, flashrom, analog system build er, and flash memory system builder http://www.microsemi.com/s oc/documents/genguide_ug.pdf silicon sculptor ii user?s guide http://www.microsemi.com/soc/doc uments/silisculptii_sculpt3_ug.pdf white paper design security in nonvolatile flash and antifuse fpgas http://www.microsemi.com/soc/ documents/designsecurity_wp.pdf understanding actel anti fuse device security http://www.microsemi.com/soc/ documents/designsecurity_wp.pdf miscellaneous libero ide flow diagram http://www.microsemi.com/soc/products/tools/libero/flow.html
revision 18 2-1 2 ? detailed specifications operating conditions table 2-1 lists the absolute maximum ratings of axcelerator devices. stresses beyond the ratings may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. devices shoul d not be operated outside the recommendations in table 2-2 . power-up/down sequence all axcelerator i/os are tristated during power-up until normal device operating conditions are reached, when i/os enter user mode. vccda should be powered up before (or coincidentally with) vcca and vcci to ensure the behavior of user i/os at system start-up. conversely, vccda should be powered down after (or coincidentally with) vcca and vcci. note that vcci and vcca can be powered up in any sequence with respect to each other, provided the requirement with respect to vccda is satisfied. table 2-1 ? absolute maximum ratings symbol parameter limits units vcca dc core supply voltage ?0.3 to 1.7 v vcci dc i/o supply voltage ?0.3 to 3.75 v vref dc i/o reference voltage ?0.3 to 3.75 v vi input voltage ?0.5 to 4.1 v vo output voltage ?0.5 to 3.75 v tstg storage temperature ?60 to +150 c vccda* supply voltage for differential i/os ?0.3 to 3.75 v note: * should be the maximum of all vcci. table 2-2 ? recommended operating conditions parameter range commercial industrial military units ambient temperature (t a ) 1 0 to +70 ?40 to +85 ?55 to +125 c 1.5 v core supply voltage 1.425 to 1.575 1.425 to 1.575 1.425 to 1.575 v 1.5 v i/o supply voltage 1.425 to 1.575 1.425 to 1.575 1.425 to 1.575 v 1.8 v i/o supply voltage 1.71 to 1.89 1.71 to 1.89 1.71 to 1.89 v 2.5 v i/o supply voltage 2.375 to 2.625 2.375 to 2.625 2.375 to 2.625 v 3.3 v i/o supply voltage 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 v vccda supply voltage 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 v vpump supply voltage 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 v notes: 1. ambient temperature (t a ) is used for commercial and industrial grades; case temperature (t c ) is used for military grades. 2. t j max = 125c
detailed specifications 2-2 revision 18 calculating power dissipation table 2-3 ? standby current device temperature icca iccda iccbank iccpll icccp 1 iih, iil, ioz 2 units standby current (core) standby current, differential i/o standby current per i/o bank standby current per pll standby current, charge pump 2.5 v vcci 3.3 v vcci active bypassed mode ax125 typical at 25c 1.5 1.5 0.2 0.3 0.2 0.3 0.01 0.01 ma 70c 15 6 0.5 0.75 1 0.4 0.01 0.01 ma 85c 25 6 0.6 0.8 1 0.4 0.2 0.01 ma 125c 50 8 1 1.5 2 0.4 0.5 0.01 ma ax250 typical at 25c 1.5 1.4 0.25 0.4 0.2 0.3 0.01 0.01 ma 70c 30 7 0.8 0.9 1 0.4 0.01 0.01 ma 85c 40 7 0.8 1 1 0.4 0.2 0.01 ma 125c 70 9 1.3 1.8 2 0.4 0.5 0.01 ma AX500 typical at 25c 5 1.4 0.4 0.75 0.2 0.3 0.01 0.01 ma 70c 60 7 1 1.5 1 0.4 0.01 0.01 ma 85c 80 7 1 1.9 1 0.4 0.2 0.01 ma 125c 180 9 1.75 2.5 1.5 0.4 0.5 0.01 ma ax1000 typical at 25c 7.5 1.5 0.5 1.25 0.2 0.3 0.01 0.01 ma 70c 80 8 1.5 3 1 0.4 0.01 0.01 ma 85c 120 8 1.5 3.4 1 0.4 0.2 0.01 ma 125c 200 10 3 4 1.5 0.4 0.5 0.01 ma ax2000 typical at 25c 20 1.6 0.7 1.5 0.2 0.3 0.01 0.01 ma 70c 160 10 2 7 1 0.4 0.01 0.01 ma 85c 200 10 3 8 1 0.4 0.2 0.01 ma 125c 500 15 4 10 1.5 0.4 0.5 0.01 ma notes: 1. icccp active is the iccda or the in ternal charge pump current. icccp bypa ssed mode is the ex ternal charge pump current iih (vpump pin). 2. iih, iil, or ioz values are measured with inputs at the same level a s v cci for iih and gnd for iil and ioz.
axcelerator family fpgas revision 18 2-3 table 2-4 ? default cload/vcci c load (pf) vcci (v) pload (mw/mhz) p10 (mw/mhz) pi/o (mw/mhz)* single-ended without vref lvttl 24 ma high slew 35 3.3 381.2 267.5 648.7 lvttl 16 ma high slew 35 3.3 381.2 225.1 606.3 lvttl 12 ma high slew 35 3.3 381.2 165.9 547.1 lvttl 8 ma high slew 35 3.3 381.2 130.3 511.5 lvttl 24 ma low slew 35 3.3 381.2 169.2 550.4 lvttl 16 ma low slew 35 3.3 381.2 150.8 532.0 lvttl 12 ma low slew 35 3.3 381.2 138.6 519.8 lvttl 8 ma low slew 35 3.3 381.2 118.7 499.9 lvcmos ? 25 35 2.5 218.8 148.0 366.8 lvcmos ? 18 35 1.8 113.4 73.4 186.8 lvcmos ? 15 (jesd8-11) 35 1.5 78.8 49.5 128.3 pci 10 3.3 108.9 218.5 327.4 pci-x 10 3.3 108.9 162.9 271.8 single-ended with vref hstl-i 20 1.5 ? 40.9 40.9 sstl2-i 30 2.5 ? 171.2 171.2 sstl2-ii 30 2.5 ? 147.8 147.8 sstl3-i 30 3.3 ? 327.2 327.2 sstl3-ii 30 3.3 ? 288.4 288.4 gtlp ? 25 10 2.5 ? 61.5 61.5 gtlp ? 33 10 3.3 ? 68.5 68.5 differential lvpecl ? 33 n/a 3.3 ? 260.6 260.6 lvds ? 25 n/a 2.5 ? 145.8 145.8 note: *p i/o = p10 + c load * vcc i 2
detailed specifications 2-4 revision 18 ptotal = pdc + pac p hclk = (p1 + p2 * s + p3 * sqrt[s]) * fs pclk = (p4 + p5 * s + p6 * sqrt[s]) * fs pr-cells = p7 * ms * fs pc-cells = p8 * mc * fs pinputs = p9 * pi * fpi table 2-5 ? different components contributing to the to tal power consumption in axcelerator devices component definition device specific value (in w/mhz) ax125 ax250 AX500 ax1000 ax2000 p1 core tile hclk power component 33 49 71 130 216 p2 r-cell power component 0.2 0.2 0.2 0.2 0.2 p3 hclk signal power dissipation 4.5 4.5 9 13.5 18 p4 core tile rclk power component 33 49 71 130 216 p5 r-cell power component 0.3 0.3 0.3 0.3 0.3 p6 rclk signal power dissipation 6.5 6.5 13 19.5 26 p7 power dissipation due to the switching activity on the r-cell 1.6 1.6 1.6 1.6 1.6 p8 power dissipation due to the switching activity on the c-cell 1.4 1.4 1.4 1.4 1.4 p9 power component associated with the input voltage 10 10 10 10 10 p10 power component associat ed with the output voltage see table per pin contribution p11 power component associated with the read operation in the ram block 25 25 25 25 25 p12 power component associated with the write operation in the ram block 30 30 30 30 30 p13 core pll power component 1.5 1.5 1.5 1.5 1.5 p dc = icca * vcca p ac =p hclk + p clk + p r-cells + p c-cells + p inputs + p outputs + p memory + p pll s = the number of r-cells clocked by this clock fs = the clock frequency s = the number of r-cells clocked by this clock fs = the clock frequency ms = the number of r-cells switching at each fs cycle fs = the clock frequency mc = the number of c-cells switching at each fs cycle fs = the clock frequency pi = the number of inputs f pi = the average input frequency
axcelerator family fpgas revision 18 2-5 poutputs = pi/o * po * fpo pmemory = p11 * nblock * frclk + p12 * nblock * fwclk ppll = p13 * fclk power estimation example this example employs an ax1000 shift-register des ign with 1,080 r-cells, one c-cell, one reset input, and one lvttl 12 ma output, with high slew. this design uses one hclk at 100 mhz. c load = the output load (technology dependent) vcci = the output voltage (technology dependent) po = the number of outputs f po = the average output frequency n block = the number of ram/fifo blocks (1 block = 4k) f rclk = the read-clock frequency of the memory f wclk = the write-clock frequency of the memory f refclk = the clock frequency of the clock input of the pll f clk = the clock frequency of the first clock output of the pll ms = 1,080 (in a shift register - 100% of r-cells are toggling at each clock cycle) fs = 100 mhz s = 1080 => p hclk = (p1 + p2 * s + p3 * sqrt[s]) * fs = 79 mw and fs = 100 mhz => p r-cells = p7 * ms * fs = 173 mw mc = 1 (1 c-cell in this shift-register) and fs = 100 mhz => p c-cells = p8 * mc * fs = 0.14 mw f pi ~ 0 mhz and pi= 1 (1 reset input => this is why f pi =0) => p inputs = p9 * pi * f pi = 0 mw f po = 50 mhz and po = 1 => p outputs = p i/o * po * f po = 27.10 mw no ram/fifo in this shift-register => p memory = 0 mw no pll in this shift-register => p pll = 0 mw p ac = p hclk + p clk + p r-cells + p c-cells + p inputs + p outputs + p memory + p pll = 276 mw p dc = 7.5ma * 1.5v = 11.25 mw p total = p dc + p ac = 11.25 mw + 276mw = 290.30 mw
detailed specifications 2-6 revision 18 thermal characteristics introduction the temperature variable in microsemi?s designer soft ware refers to the junction temperature, not the ambient temperature. this is an important distin ction because dynamic and static power consumption cause the chip junction temperature to be higher than the ambient temperature. eq 1 can be used to calculate junction temperature. t j = junction temperature = t + t a eq 1 where: t = ja * p eq 2 where: package thermal characteristics the device junction-to-case thermal characteristic is jc , and the junction-to-ambient air characteristic is ja . the thermal char acteristics for ja are shown with two different air flow rates. jc values are provided for reference. the absolute maximum junction temperature is 125 c. the maximum power dissipation allowed for commercial- and industrial-grade devices is a function of ja . a sample calculation of the absolute maximum power dissipation allowed for an 896-pin fbga package at commercial temperature and still air is as follows: t a = ambient temperature t= temperature gradient between j unction (silicon) and ambient p =power ja = junction to ambient of package. ja numbers are located under table 2-6 on page 2-7 . maximum power allowed max. junction temp. ( c) max. ambient temp. ( c) ? ja ( c/w) ------------------------------------------------------------------------------------------------------------------------------- ------------------ - 125 c70 c ? 13.6 c/w --------------------------------------- 4.04 w = = =
axcelerator family fpgas revision 18 2-7 the maximum power dissipation allowed for military temperature and mil-std 883b devices is specified as a function of jc . timing characteristics axcelerator devices are manufactured in a cmos process, therefore, device performance varies according to temperature, voltage, and process vari ations. minimum timing para meters reflect maximum operating voltage, minimum operating temperatur e, and best-case processing. maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. the derating factors shown in ta b l e 2 - 7 should be applied to all timing data contained within this datasheet. all timing numbers listed in this datasheet represent sample timing characteristi cs of axcelerator devices. actual timing delay values are design-specific and can be derived from the timer tool in microsemi?s designer software after place-and-route. table 2-6 ? package thermal characteristics package type pin count jc ja still air ja 1.0m/s ja 2.5m/s units chip scale package (csp) 180 n/a 57.8 51.0 50 c/w plastic quad flat pack (pqfp) 208 8.0 26 23.5 20.9 c/w plastic ball grid array ( pbga) 729 2.2 13.7 10.6 9.6 c/w fine pitch ball grid array (fbga) 256 3.0 26.6 22.8 21.5 c/w fine pitch ball grid array (fbga) 324 3.0 25.8 22.1 20.9 c/w fine pitch ball grid array (fbga) 484 3.2 20.5 17.0 15.9 c/w fine pitch ball grid array (fbga) 676 3.2 16.4 13.0 12.0 c/w fine pitch ball grid array (fbga) 896 2.4 13.6 10.4 9.4 c/w fine pitch ball grid array (fbga) 1152 1.8 12.0 8.9 7.9 c/w ceramic quad flat pack (cqfp) 1 208 2.0 22 19.8 18.0 c/w ceramic quad flat pack (cqfp) 1 352 2.0 17.9 16.1 14.7 c/w ceramic column grid array (ccga) 2 624 6.5 8.9 8.5 8 c/w notes: 1. jc for the 208-pin and 352-pin cqfp refers to the thermal resistance between the junction and the bottom of the package. 2. jc for the 624-pin ccga refers to the thermal resistance between the junction and the top surface of the package. thermal resistance from junction to board ( jb ) for ccga 624 package is 3.4 c/w. table 2-7 ? temperature and voltage timing derating factors (normalized to wors t-case commercial, t j = 70c, vcca = 1.425v) vcca junction temperature ?55c ?40c 0c 25c 70c 85c 125c 1.4 v 0.83 0.86 0.91 0.96 1.02 1.05 1.15 1.425 v 0.82 0.84 0.90 0.94 1.00 1.04 1.13 1.5 v 0.78 0.80 0.85 0.89 0.95 0.98 1.07 1.575 v 0.74 0.76 0.81 0.85 0.90 0.94 1.02 1.6 v 0.73 0.75 0.80 0.84 0.89 0.92 1.01 notes: 1. the user can set the junction temperature in designer software to be any integer value in the range of ? 55 c to 175 c. 2. the user can set the core voltage in designer software to be any value between 1.4v and 1.6v.
detailed specifications 2-8 revision 18 timing model hardwired clock ? using lvttl 24 ma high slew clock i/o routed clock ? using lvttl 24 ma high slew clock i/o note: worst case timing data for the ax1000, ?2 speed grade figure 2-1 ? worst case timing data combinatorial cell combinatorial cell combinatorial cell combinatorial cell dq dq dq y fco + + routed clock register cell lvpecl lvpecl lvds register cell hardwired or routed clock hardwired clock i/o module i/o module (registered) i/o module (nonregistered) i/o module (non- registered) i/o module (nonregistered) y buffer module buffer module buffer module carry chain i/o i/o lvttl output drive strength = 4 (24 ma) high slew rate t hckh = 3.03 ns f max (external) = 350 mhz f max (internal) = 870 mhz t sud = 0.23 ns t icklq = 0.67 ns t dp = 1.66 ns t rd2 = 0.53 ns t dp = 1.80 ns t hckl = 3.02 ns t rckl = 3.08 ns t rco = 0.67 ns t sud = 0.23 ns t rd1 = 0.45 ns t pd = 0.74 ns t rckl = 3.08 ns f max (external) = 350 mhz f max (internal) = 870 mhz t rco = 0.67 ns t sud = 0.23 ns t bpfd = 0.12 ns t py = 1.13 ns gtl + 3.3 v t ioclky = 0.67 ns t sud = 0.23 ns t bfpd = 0.12 ns t pd = 0.74 ns t bfpd = 0.12 ns t pdc = 0.57 ns t ccy = 0.61 ns t py = 2.99 ns t py = 2.24 ns t rd1 = 0.45 ns t rd2 = 0.53 ns t rd3 = 0.56 ns external setup = (t dp + t rd2 + t sud) ? t hckl = (1.72 + 0.53 + 0.23) ? 3.02 = ?0.54 ns clock-to-out (pad-to-pad) = t hckl + t rco + t rd1 + t py = 3.02 + 0.67 + 0.45 + 2.99 = 7.13 ns external setup = (t dp + t rd2 + t sud) ? t rckh = (1.72 + 0.53 + 0.23) ? 3.13 = ?0.65 ns clock-to-out (pad-to-pad) = t rckh + t rco + t rd1 + t py = 3.13 + 0.67 + 0.45 + 3.03 = 7.24 ns
axcelerator family fpgas revision 18 2-9 i/o specifications pin descriptions supply pins gnd ground low supply voltage. vcca supply voltage supply voltage for array (1.5v). see "operating conditions" on page 2-1 for more information. vccibx supply voltage supply voltage for i/os. bx is the i/o bank id ? 0 to 7. see "operating conditions" on page 2-1 for more information. vccda supply voltage supply voltage for the i/o differential am plifier and jtag and probe interfaces. see "operating conditions" on page 2-1 for more information. vccda should be tied to 3.3v. vccpla/b/c/d/e/f/g/h supply voltage pll analog power supply (1.5v) for internal pll. there are eight in each device. vccpla supports the pll associated with global resource hclka, vccplb supports the pll associated with global resource hclkb, etc. the pll analog power supply pins should be connected to 1.5v whether pll is used or not. vcompla/b/c/d/e/f/ g/h supply voltage compensation reference signals for inter nal pll. there are eight in each device. vcompla supports the pll associated with global resource hclka, vcomple supports the pll associated with global resource clke, etc. (see figure 2-2 on page 2-9 for correct external connection to the supply). the vcomplx pins should be left floating if pll is not used. vpump supply voltag e (external pump) in the low power mode, vpump will be used to access an external charge pump (if the user desires to bypass the internal charge pump to further reduce po wer). the device starts using the external charge pump when the voltage level on vpump reaches vih 1 . in normal device operation, when using the internal charge pump, vpump should be tied to gnd. 1. when v pump = v ih , it shuts off the internal charge pump. see "low power mode" on page 2-106 . figure 2-2 ? vccplx and vcomplx po wer supply connect 1.5 v supply axcelerator chip 0.1 f 10 f 250 vccplx vcomplx
detailed specifications 2-10 revision 18 user-defined supply pins vref supply voltage reference voltage for i/o banks. vref pins are config ured by the user from regular i/o pins; vref pins are not in fixed locations. there can be one or more vref pins in an i/o bank. global pins hclka/b/c/d dedicated (hardwir ed) clocks a, b, c and d these pins are the clock inputs for sequential modules or north plls. input levels are compatible with all supported i/o standards. there is a p/n pin pair fo r support of differential i/o standards. single-ended clock i/os can only be assigned to the p side of a paired i/o. this input is directly wired to each r-cell and offers clock speeds independent of the number of r-cells being driven. when the hclk pins are unused, it is recommended that they are tied to ground. clke/f/g/h routed clocks e, f, g, and h these pins are clock inputs for clock distribution netwo rks or south plls. input levels are compatible with all supported i/o standards. there is a p/n pin pair for support of differential i/o standards. single-ended clock i/os can only be assigned to the p side of a paired i/o. the clock input is buffered prior to clocking the r-cells. when the clk pins are unused, micros emi recommends that they are tied to ground. jtag/probe pins pra/b/c/d probe a, b, c and d the probe pins are used to output data from any user-defined design node wit hin the device (controlled with silicon explorer ii). these independent diagnos tic pins can be used to allow real-time diagnostic output of any signal path within the device. the pins? probe capabilities can be permanently disabled to protect programmed design confidentiality. th e probe pins are of lvttl output levels. tck test clock test clock input for jtag boundary-scan testi ng and diagnostic probe (silicon explorer ii). tdi test data input serial input for jtag boundary-scan testing and dia gnostic probe. tdi is equipped with an internal 10 k pull-up resistor. tdo test data output serial output for jtag boundary-scan testing. tms test mode select the tms pin controls the use of the ieee 1149.1 boundary-scan pins (tck, tdi, tdo, trst). tms is equipped with an internal 10 k pull-up resistor. trst boundary scan reset pin the trst pin functions as an active-low input to asynchronously initialize or reset the boundary scan circuit. the trst pin is equipped with a 10 k pull-up resistor. special functions lp low power pin the lp pin controls the low power mode of axcelera tor devices. the device is placed in the low power mode by connecting the lp pin to logic high. to ex it the low power mode, the lp pin must be set low. additionally, the lp pin must be set low during chip powering-up or chip powering-down operations. see "low power mode" on page 2-106 for more details. nc no connection this pin is not connected to circuitry within the devic e. these pins can be driven to any voltage or can be left floating with no effect on the operation of the device.
axcelerator family fpgas revision 18 2-11 user i/os 2 introduction the axcelerator family features a flexible i/o stru cture, supporting a range of mixed voltages (1.5 v, 1.8 v, 2.5 v, and 3.3 v) with its bank-selectable i/os. table 2-8 on page 2-12 contains the i/o standards supported by the axcelerator family, and table 2-10 on page 2-12 compares the features of the different i/o standards. each i/o provides programmable slew rates, dr ive strengths, and weak pull-up and weak pull-down circuits. the slew rate setting is effective for both rising and falling edges. i/o standards, except 3.3 v pci and 3.3 v pci-x, are capable of hot insertion. 3.3 v pci and 3.3 v pci- x are 5 v tolerant with the aid of an external resistor. the input buffer has an optional user-configurable del ay element. the element can reduce or eliminate the hold time requirement for input signals registered within the i/o cell. the value for the delay is set on a bank-wide basis. note that the delay will be a function of process va riations as well as temperature and voltage changes. each i/o includes three registers: an input (inreg), an output (outreg), and an enable register (enreg). i/os are organized into banks, and there ar e eight banks per device?two per side ( figure 2-6 on page 2-18 ). each i/o bank has a common vc ci, the supply voltage for its i/os. for voltage-referenced i/os, each bank also has a common reference-voltage bus, vref. while vref must have a common voltage for an entire i/o bank, its location is user-selectable. in other words, any user i/o in the bank can be selected to be a vref. the location of the vref pin should be selected according to the following rules: ? any pin that is assigned as a vref can control a maximum of eight user i/o pad locations in each direction (16 total maximum) within the same i/o bank. ? i/o pad locations listed as no connects are count ed as part of the 16 maximum. in many cases, this leads to fewer than eight user i/o package pins in each direction being controlled by a vref pin. ? dedicated i/o pins such as gnd and vcci are counted as part of the 16. ? the two user i/o pads immediately adjacent on each side of the vref pin (four in total) may only be used as inputs. the exception is when there is a vcci/gnd pair separating the vref pin and the user i/o pad location. ? the user does not need to assign vref pins for outbuf and tribuf. vref pins are needed only for input and bidirectional i/os. the differential amplifier supply voltage vccda should be connected to 3.3 v. a user can gain access to the various i/o standards in three ways: ? instantiate specific library macros that represent the desired specific standard. ? use generic i/o macros and then use designer?s pineditor to specify the desired i/o standards (please note that this is not app licable to differential standards). ? a combination of the first two methods. refer to the i/o features in axcelerator family devices application note and the antifuse macro library guide for more details. 2. do not use an external resister to pull the i/o above v cci for a higher logic ?1? voltage level. the desired higher logic ?1? voltage level will be degraded due to a small i/o curren t, which exists when the i/o is pulled up above v cci .
detailed specifications 2-12 revision 18 table 2-8 ? i/o standards supported by the axcelerator family i/o standard input/output supply voltage (vcci) input reference voltage (vref) board termination voltage (vtt) lvttl 3.3 n/a n/a lvcmos 2.5 v 2.5 n/a n/a lvcmos 1.8 v 1.8 n/a n/a lvcmos 1.5 v (jdec8-11) 1.5 n/a n/a 3.3v pci/pci-x 3.3 n/a n/a gtl+ 3.3 v 3.3 1.0 1.2 gtl+ 2.5 v * 2.5 1.0 1.2 hstl class 1 1.5 0.75 0.75 sstl3 class 1 and ii 3.3 1.5 1.5 sstl2 class1 and ii 2.5 1.25 1.25 lvds 2.5 n/a n/a lvpecl 3.3 n/a n/a note: *2.5 v gtl+ is not suppor ted across the full mili tary temperature range. table 2-9 ? supply voltages vcca vcci input tolerance output drive level 1.5 v 1.5 v 3.3 v 1.5 v 1.5 v 1.8 v 3.3 v 1.8 v 1.5 v 2.5 v 3.3 v 2.5 v 1.5 v 3.3 v 3.3 v 3.3 v table 2-10 ? i/o features comparison i/o assignment clamp diode hot insertion 5 v tolerance input buffer output buffer lvttl no yes yes 1 enabled/disabled 3.3 v pci, 3.3 v pci-x yes no yes 1, 2 enabled/disabled lvcmos 2.5 v no yes no enabled/disabled lvcmos 1.8 v no yes no enabled/disabled lvcmos 1.5 v (jesd8-11) no yes no enabled/disabled voltage-referenced input buffer no yes no enabled/disabled differential, lvds/lvpecl, input no yes no enabled disabled 3 differential, lvds/lvpecl, ou tput no yes no disabled enabled 4 notes: 1. can be implemented with an idt bus switch. 2. can be implemented with an external resistor. 3. the oe input of the output buffer must be deasserted permanently (handled by software). 4. the oe input of the output buffer must be asserted permanently (handled by software).
axcelerator family fpgas revision 18 2-13 5v tolerance there are two schemes to achieve 5 v tolerance: 1. 3.3 v pci and 3.3 v pci-x are the only i/o sta ndards that directly allow 5 v tolerance. to implement this, an internal clamp diode between the input pad and the vcci pad is enabled so that the voltage at the input pin is clamped, as shown in eq 3 : vinput = vcci + vdiode = 3.3 v + 0.7 v = 4.0 v eq 3 the internal vcci clamp diode is only enabled while the device is powered on, so the voltage at the input will not be clamped if the vcci or vcca are pow ered off. an external series resistor (~100 ? ) is required between the input pin and the 5 v signal source to limit the current to less than 20 ma ( figure 2-3 ). the 100 ? resistor was chosen to meet the input tr/tf requirement ( table 2-19 on page 2-21 ). the gnd clamp diode is available for all i/o standards and always enabled. 2. 5 v tolerance can also be achieved with 3.3 v i/o standards (3.3 v pci, 3.3 v pci-x, and lvttl) using a bus-switch product (e.g. id tqs32x2384). this will convert the 5 v signal to a 3.3 v signal with minimum delay ( figure 2-4 ). simultaneous switch ing outputs (sso) when multiple output drivers switch simultaneously , they induce a voltage drop in the chip/package power distribution. this simultaneous switching mo mentarily raises the ground voltage within the device relative to the system ground. this apparent shift in the ground potential to a non-zero value is known as simultaneous switching noise (ssn) or more commonly, ground bounce. ssn becomes more of an issue in high pin count packages and when using high performance devices such as the axcelerator family. based upon testing, microsemi recommends that users not exceed eight simultaneous switching outputs (sso) per each vcci/gnd pair. to ease this potential burden on designers, microsemi has designed all of the axcelerator bgas 3 to not exceed this limit with the exception of the cs180, wh ich has an i/o to vcci/gnd pair ratio of nine to one. please refer to the simultaneous switching noise and signal integrity application note for more information. figure 2-3 ? use of an external resistor for 5 v tolerance figure 2-4 ? bus switch idtqs32x2384 3. the user should note that in bank 8 of both ax1000-fg484 and AX500-fg484, there are local violations of this 8:1 ratio. non-microsemi part mirosemi fpga 5 v 3.3 v 3.3 v vcci clamp diode r ext gnd clamp diode 5 v 3.3 v 3.3 v 20x 5 v
detailed specifications 2-14 revision 18 i/o banks and compatibility since each i/o bank has its own user-assigned input reference voltage (vref) and an input/output supply voltage (vcci), only i/os with compatible standards can be assigned to the same bank. table 2-11 shows the compatible i/o standards for a comm on vref (for voltage-referenced standards). similarly, table 2-12 shows compatible standards for a common vcci. table 2-11 ? compatible i/o standards for different vref values vref compatible standards 1.5 v sstl 3 (class i and ii) 1.25 v sstl 2 (class i and ii) 1.0 v gtl+ (2.5v and 3.3v outputs) 0.75 v hstl (class i) table 2-12 ? compatible i/o standards for different vcci values vcci 1 compatible standards vref 3.3 v lvttl, pci, pci-x, lvpecl, gtl+ 3.3 v 1.0 3.3 v sstl 3 (class i and ii), lvttl, pci, lvpecl 1.5 2.5 v lvcmos 2.5 v, gtl+ 2.5 v, lvds 2 1.0 2.5 v lvcmos 2.5 v, sstl 2 (classes i and ii), lvds 2 1.25 1.8 v lvcmos 1.8 v n/a 1.5 v lvcmos 1.5 v, hstl class i 0.75 notes: 1. vcci is used for both inputs and outputs 2. vcci tolerance is 5%
axcelerator family fpgas revision 18 2-15 table 2-13 summarizes the different combinations of voltages and i/o standards that can be used together in the same i/o bank. note that two i/o standards are compatible if: ? their vcci values are identical. ? their vref standards are identical (if applicable). for example, if lvttl 3.3 v (vref= 1.0 v) is us ed, then the other available (i.e. compatible) i/o standards in the same bank are lvttl 3.3 v pci/pci-x, gtl+, and lvpecl. also note that when multiple i/o standards are used within a bank, the voltage tolerance will be limited to the minimum tolerance of all i/o standards used in the bank. table 2-13 ? legal i/o usage matrix i/o standard lvttl 3.3 v lvcmos 2.5 v lvcmos1.8 v lvcmos1.5 v (jesd8-11) 3.3v pci/pci-x gtl + (3.3 v) gtl + (2.5 v) hstl class i (1. 5v) sstl2 class i & ii (2.5 v) sstl3 class i & ii (3.3 v) lvds (2.5 v) lvpecl (3.3 v) lvttl 3.3 v (vref=1.0 v) 3 ??? 33 ????? 3 lvttl 3.3 v(vref=1.5 v) 3 ??? 3 ???? 3 ? 3 lvcmos 2.5 v (vref=1.0 v) ? 3 ??? ? 3 ??? 3 ? lvcmos 2.5 v (vref=1.25v) ? 3 ??? ? ? ? 3 ? 3 ? lvcmos1.8 v ? ? 3 ?? ? ? ? ??? ? lvcmos1.5 v (vref = 1.75 v) (jesd8-11) ? ? ? 3 ?? ? 3 ???? 3.3 v pci/pci-x (vref = 1.0 v) 3 ??? 33 ????? 3 3.3 v pci/pci-x (vref= 1.5 v) 3 ??? 3 ???? 3 ? 3 gtl + (3.3 v) 3 ??? 33 ????? 3 gtl + (2.5 v) ? 3 ??? ? 3 ????? hstl class i ? ? ? 3 ?? ? 3 ???? sstl2 class i & ii ? 3 ??? ? ? ? 3 ? 3 ? sstl3 class i & ii 3 ??? 3 ???? 3 ? 3 lvds (vref = 1.0 v) ? 3 ??? ? 3 ??? 3 ? lvds (vref = 1.25 v) ? 3 ??? ? ? ? 3 ? 3 ? lvpecl (vref = 1.0 v) 3 ??? 33 ????? 3 lvpecl (vref = 1.5 v) 3 ??? 3 ???? 3 ? 3 notes: 1. note that gtl+ 2.5 v is not supported across the full military temperature range. 2. a " ? " indicates whether standards can be used within a bank at the same time. examples: a) lvttl can be used with 3. 3v pci and gtl+ (3.3v), when v ref = 1.0v (gtl+ requirement). b) lvttl can be used with 3.3v pc i and sstl3 class i and ii, when v ref = 1.5v (sstl3 requirement).
detailed specifications 2-16 revision 18 i/o clusters each i/o cluster incorporates two i/o modules, four rx modules, two tx modules, and a buffer module. in turn, each i/o module contains one input regist er (inreg), one output register (outreg), and one enable register (enreg) ( figure 2-5 ). using an i/o register to access the i/o registers, registers must be instant iated in the netlist and t hen connected to the i/os. usage of each i/o register (register combining) is in dividually controlled and can be selected/deselected using the pineditor tool in the designer software. i/o register combining can also be controlled at the device level, affecting all i/os. please note, the i/o r egister option is deselected by default in any given design. 4 in addition, designer software provides a global option to enable/disable the usage of registers in the i/os. this option is design-specific. the setting for each individual i/o overrides this global option. furthermore, the global set fuse option in the designer software, w hen checked, causes all i/o registers to output logic high at device power-up. figure 2-5 ? i/o cluster interface enreg din yout y dcin outreg din yout inreg i/o cluster fpga logic core oep uop uip programmable delay slew rate i/o oen uon uin drive strength p pad n pad routed input track routed input track output track routed input track routed input track output track routed input track routed input track output track enreg din yout y dcin outreg din yout inreg routed input track routed input track output track programmable delay slew rate i/o drive strength vref vref bsr bsr 4. please note that register combining for multi fanout nets is not supported.
axcelerator family fpgas revision 18 2-17 using the weak pull-up and pull-down circuits each axcelerator i/o comes with a weak pu ll-up/down circuit (on the order of 10 k ). these are weak transistors with the gates tied on, so the on resistance of the transistor emulates a resistor. the weak pull-up and pull-down is active only when the device is powered up, and they must be biased to be on. when the rails are coming up, they are not biased full y, so they do not behave as resistors until the voltage is at sufficient levels to bias the transistor s. the key is they really are transistors; they are not traces of poly silicon, which is anot her way to do an on-chip resistor (those take much more room). i/o macros are provided for combinations of pull up /down for lvttl, lvcmos (2.5 v, 1.8 v, and 1.5 v) standards. these macros can be instantiated if a k eeper circuit for any input buffer is required. customizing the i/o ? a five-bit programmable input delay element is a ssociated with each i/o. the value of this delay is set on a bank-wide basis ( table 2-14 ). it is optional for each input buffer within the bank (i.e. the user can enable or disable the delay element for the i/o). when the input buffer drives a register within the i/o, the delay element is activated by default to ensure a zero hold-time. the default setting for this property can be set in designer. when the input buffer does not drive a register, the delay element is deactivated to provide higher performance. again, this can be overridden by changing the default setting for this property in designer. ? the slew-rate value for the lvttl output buffer can be programmed and can be set to either slow or fast. ? the drive strength value for lvttl output buf fers can be programmed as well. there are four different drive strength values ? 8 ma, 12 ma, 16 ma, or 24 ma ? that can be specified in designer. 5 table 2-14 ? bank-wide delay values bits setting delay (ns) bits setting delay (ns) 00.54162.01 10.65172.13 20.71182.19 30.83192.3 4 0.9 20 2.38 51.01212.49 61.08222.55 71.19232.67 81.27242.75 91.39252.87 10 1.45 26 2.93 11 1.56 27 3.04 12 1.64 28 3.12 13 1.75 29 3.23 14 1.81 30 3.29 15 1.93 31 3.41 note: delay values are approximate and will vary with process, temperature, and voltage. 5. these values are minimum drive strengths.
detailed specifications 2-18 revision 18 using the differential i/o standards differential i/o macros should be instantiated in th e netlist. the settings for these i/o standards cannot be changed inside designer. note that there are no tris tated or bidirectional i/o buffers for differential standards. using the voltage-referenced i/o standards using these i/o standards is simila r to that of single-ended i/o standards. their settings can be changed in designer. using ddr (double data rate) in double data rate mode, new data is present on every transition of the clock signal. clock and data lines have identical bandwidth and signal integrity re quirements, making it very efficient for implementing very high-speed systems. to implement a ddr, users need to: 1. instantiate an input buffer (with the required i/o standard) 2. instantiate the ddr_reg macro ( figure 2-6 ) 3. connect the output from the input buffer to the input of the ddr macro macros for specific i/o standards there are different macro types for any i/o standard or feature that determi ne the required vcci and vref voltages for an i/o. the generic buffer macros require the lvttl standard with slow slew rate and 24 ma-drive strength. lvttl can support high slew rate but this should only be used for critical signals. most of the macro symbols represent vari ations of the six generic symbol types: ? clkbuf: clock buffer ? hclkbuf: hardwired clock buffer ? inbuf: input buffer ? outbuf: output buffer ? tribuf: tristate buffer ? bibuf: bidirectional buffer other macros include the following: ? differential i/o standard macros: the lvds and lvpecl macros eit her have a pair of differential inputs (e.g. inbuf_lvds) or a pair of differential outputs (e.g. outbuf_lvpecl). ? pull-up and pull-down variations of the inbuf, bibuf, and tribuf macros. these are available only with ttl and lvcmos thresholds. they c an be used to model the behavior of the pull-up and pull-down resistors available in the architec ture. whenever an input pin is left unconnected, the output pin will either go high or low rather than unknown. this allows users to leave inputs unconnected without having the negative effe ct on simulation of propagating unknowns. ? ddr_reg macro. it can be connected to any i/o standard input buffers (i.e. inbuf) to implement a double data rate register. designer software will map it to the i/o module in the same way it maps the other registers to the i/o module. figure 2-6 ? ddr register dqr qf d clr pset clk
axcelerator family fpgas revision 18 2-19 table 2-15 , ta b l e 2 - 1 6 , and ta b l e 2 - 1 7 list all the available macro names differentiated by i/o standard, type, slew rate, and drive strength. table 2-15 ? macros for single-e nded i/o standards standard vcci macro names lvttl 3.3 v clkbuf, hclkbuf inbuf, outbuf, outbuf_s_8, outbuf_s_12, outbuf_s_16, outbuf_s_24, outbuf_h_8, outbuf_h_12, outbuf_h_16, outbuf_h_24, tribuf, tribuf_s_8, tribuf_s_1 2, tribuf_s_16, tribuf_s_24, tribuf_h_8, tribuf_h_12, tribuf_h_16, tribuf_h_24, bibuf, bibuf_s_8, bibuf_s _12, bibuf_s_16, bibuf_s_24, bibuf_h_8, bibuf_h_12, bibuf_h_16, bibuf_h_24 3.3 v pci 3.3 v clkbuf_pci, hclkbu f_pci, inbuf_pci, outbuf_pci, tribuf_pci, bibuf_pci 3.3 v pci-x 3.3 v clkbuf_pci-x, hclkbuf_ pci-x, inbuf_pci-x, outbuf_pci-x, tribuf_pci-x, bibuf_pci-x lvcmos25 2.5 v clkbuf_lvcmos25, hclkbuf_lvcmos25, inbuf_lvcmos25, outbuf_lvcmos25, tribuf_l vcmos25, bibuf_lvcmos25 lvcmos18 1.8 v clkbuf_lvcmos18, hclkbuf_lvcmos18, inbuf_lvcmos18, outbuf_lvcmos18, tribuf_l vcmos18, bibuf_lvcmos18 lvcmos15 (jesd8-11) 1.5 v clkbuf_lvcmos15, hclkbuf_lvcmos15, inbuf_lvcmos15, outbuf_lvcmos15, tribuf_l vcmos15, bibuf_lvcmos15 table 2-16 ? i/o macros for differential i/o standards standard vcci macro names lvpecl 3.3 v clkbuf_lvpecl, hclkbuf_ lvpecl, inbuf_lvpecl, outbuf_lvpecl lvds 2.5 v clkbuf_lvds, hclkbuf_lvds, inbuf_lvds, outbuf_lvds table 2-17 ? i/o macros for voltage-referenced i/o standards standard vcci vref macro names gtl+ 3.3 v 1.0 v clkbuf_gtp33, hclkbuf_gtp33, inbuf_gtp33, outbuf_gtp33, tribuf _gtp33, bibuf_gtp33 gtl+ 2.5 v 1.0 v clkbuf_gtp25, hclkbuf_gtp25, inbuf_gtp25, outbuf_gtp25, tribuf _gtp25, bibuf_gtp25 sstl2 class i 2.5 v 1.25 v clkbuf_sstl2_i, hclkbuf_ sstl2_i, inbuf_sstl2_i, outbuf_sstl2_i, tribuf _sstl2_i, bibuf_sstl2_i sstl2 class ii 2.5 v 1.25 v clkbuf_sstl2_ ii, hclkbuf_sstl2_i i, inbuf_sstl2_ii, outbuf_sstl2_ii, tribuf _sstl2_ii, bibuf_sstl2_ii sstl3 class i 3.3 v 1.5 v clkbuf_sst l3_i, hclkbuf_sstl3_i, inbuf_sstl3_i, outbuf_sstl3_i, tribuf _sstl3_i, bibuf_sstl3_i sstl3 class ii 3.3 v 1.5 v clkbuf_sstl3_ ii, hclkbuf_sstl3_i i, inbuf_sstl3_ii, outbuf_sstl3_ii, tribuf _sstl3_ii, bibuf_sstl3_ii hstl class i 1.5 v 0.75 v clkbuf_hstl_i, hclkbuf_hstl_i, inbuf_hstl_i, outbuf_hstl_i, tribuf_hstl_i, bibuf_hstl_i
detailed specifications 2-20 revision 18 user i/o naming conventions due to the complex and flexible nat ure of the axcelerator family?s us er i/os, a naming scheme is used to show the details of the i/o. the naming scheme explains to which bank an i/o belongs, as well as the pairing and pin polarity for differential i/os ( figure 2-7 ). figure 2-7 ? i/o bank and dedicated pin layout figure 2-8 ? general naming schemes prc prd corner4 corner3 corner1 i/o bank 3 i/o bank 2 i/o bank 0 i/o bank 5 i/o bank 1 i/o bank 4 i/o bank 7 i/o bank 6 corner2 ax125 gnd vccda gnd vccda vpump gnd vccda gnd vccda vcomplg vcomplh vccplg vccplh vcomplb vcompla vccplb vccpla vcomple vcomplf vccple vccplf vcompld vcomplc vccpld vccplc gnd vccda gnd vccda gnd vccda gnd vccda gnd vcca gnd vcca gnd vcca gnd vcca gnd vcca gnd vcca gnd vcci2 gnd vcci1 gnd gnd vcci5 gnd vcci4 gnd vccda gnd vccda gnd vccda gnd vcca gnd vcca gnd vcci6 gnd vcci7 gnd vcci3 vcci0 prb pra tdo tdi tck tms trst lp ioxxxbxfx fx refers to an unimplemented feature and can be ignored. bank i/d 0 through 7, clockwise from iob nw p - positive pin/ n - negative pin pair number in the bank, starting at 00, clockwise from iob nw io12pb1f1 is the positive pin of the thirteenth pair of the first i/o bank (iob ne). io12pb1 combined with io12nb1 form a differential pair. for those i/os that can be employed either as a user i/o or as a special function, the following nomenclature is used: ioxxxbxfx/special_function_name ioxxpb1fx/xclkx this pin can be configured as a clock input or as a user i/o. examples:
axcelerator family fpgas revision 18 2-21 i/o standard electrical specifications table 2-18 ? input capacitance symbol parameter conditions min. max. units c in input capacitance vin = 0, f = 1.0 mhz 10 pf c inclk input capacitance on hclk and rclk pin vin = 0, f = 1.0 mhz 10 pf table 2-19 ? i/o input rise time and fall time* input buffer input rise/fall time (min.) input rise/fall time (max.) lvttl no requirement 50 ns lvcmos 2.5v no requirement 50 ns lvcmos 1.8v no requirement 50 ns lvcmos 1.5v no requirement 50 ns pci no requirement 50 ns pcix no requirement 50 ns gtl+ no requirement 50 ns hstl no requirement 50 ns sstl2 no requirement 50 ns hstl3 no requirement 50 ns lvds no requirement 50 ns lvpecl no requirement 50 ns note: *input rise/fall time applies to all inputs, be it clock or data. inputs have to ramp up/down linearly, in a monotonic way. glitches or a plateau may cause double clocking. they must be avoided. for output rise/fall time, refer to the ibis models for extraction. figure 2-9 ? input buffer delays y in inbuf pad ln y gnd input high 0 v vcca t dp t dp vtrip vtrip 50% 50% (rising) (falling)
detailed specifications 2-22 revision 18 figure 2-10 ? output buffer delays ln ln out gnd 50% 50% tribuf en en out gnd 50% 10% 50% en out gnd 50% 50% 90% to ac test loads (shown below) out pad vtt t enhz t enzh voh vtrip gnd / vtt vtt vol t enzl t enlz vcci / vtt vtrip vtrip vtrip voh t py t py (t dlh ) (t dhl ) vcca vcca vcca vol
axcelerator family fpgas revision 18 2-23 i/o module timing characteristics figure 2-11 ? timing model figure 2-12 ? input register timing characteristics outreg pre/clr enreg pre/clr inreg pre/clr clk (routed or hardwired) output register output enable register input register e e e dq d q dq e d q clr preset clk t sue t he t sud t hd t iclkq t wasyn t hasyn t clr t reasyn t cpwhl t cpwlh t preset t wasyn t hasyn t reasyn
detailed specifications 2-24 revision 18 figure 2-13 ? output register timing characteristics figure 2-14 ? output enable register timing characteristics e d q clr preset clk t sue t he t sud t hd t oclkq t wasyn t hasyn t clr t reasyn t cpwhl t cpwlh t preset t wasyn t hasyn t reasyn e d q clr preset clk t sue t he t sud t hd t oclkq t wasyn t hasyn t clr t reasyn t cpwhl t cpwlh t preset t wasyn t hasyn t reasyn
axcelerator family fpgas revision 18 2-25 3.3 v lvttl low-voltage transistor-transistor logic is a general purpose standard (eia/jesd) for 3.3 v applications. it uses an lvttl input buffer and push-pull output buffer. ac loadings table 2-20 ? dc input and output levels vil vih vol voh iol ioh min., v max., v min., v max., v max., v min., v ma ma ?0.3 0.8 2.0 3.6 0.4 2.4 24 ?24 figure 2-15 ? ac test loads table 2-21 ? ac waveforms, measuring points, and capacitive load input low (v) input high (v) meas uring point* (v) vref (typ) (v) c load (pf) 0 3.0 1.40 n/a 35 note: * measuring point = vtrip r to v cci for t plz / t pzl r to gnd for t phz / t pzh 35 pf for t pzh / t pzl 5 pf for t phz / t plz test point test point 35 pf for tristate r=1k for t pd
detailed specifications 2-26 revision 18 timing characteristics table 2-22 ? 3.3 v lvttl i/o module worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed parameter description min. max. min. max. min. max. units lvttl output drive strength = 1 (8 ma) / low slew rate t dp input buffer 1.68 1.92 2.26 ns t py output buffer 14.28 16.27 19.13 ns t enzl enable to pad delay through the output buffer?z to low 15.25 17.37 20.42 ns t enzh enable to pad delay through the output buffer?z to high 14.26 16.24 19.09 ns t enlz enable to pad delay through the output buffer?low to z 1.56 1.57 1.58 ns t enhz enable to pad delay through the output buffer?high to z 1.95 1.96 1.97 ns t ioclkq sequential clock-to-q for the i/ o input register 0.67 0.77 0.90 ns t ioclky clock-to-output y for the i/o output register and the i/o enable register 0.67 0.77 0.90 ns t sud data input set-up 0.23 0.27 0.31 ns t sue enable input set-up 0.26 0.30 0.35 ns t hd data input hold 0.00 0.00 0.00 ns t he enable input hold 0.00 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 039 ns t wasyn asynchronous pulse width 0.37 0.37 0.37 ns t reasyn asynchronous recovery time 0.13 0.15 0.17 ns t hasyn asynchronous removal time 0.00 0.00 0.00 ns t clr asynchronous clear-to-q 0.23 0.27 0.31 ns t preset asynchronous preset-to-q 0.23 0.27 0.31 ns
axcelerator family fpgas revision 18 2-27 lvttl output drive strength = 2 (12 ma) / low slew rate t dp input buffer 1.68 1.92 2.26 ns t py output buffer 12.14 13.83 16.26 ns t enzl enable to pad delay through the output buffer?z to low 12.43 14.16 16.65 ns t enzh enable to pad delay through the output buffer?z to high 12.17 13.86 16.30 ns t enlz enable to pad delay through the output buffer?low to z 1.73 1.74 1.75 ns t enhz enable to pad delay through the output buffer?high to z 2.22 2.23 2.24 ns t ioclkq sequential clock-to-q for the i/ o input register 0.67 0.77 0.90 ns t ioclky clock-to-output y for the i/o output register and the i/o enable register 0.67 0.77 0.90 ns t sud data input set-up 0.23 0.27 0.31 ns t sue enable input set-up 0.26 0.30 0.35 ns t hd data input hold 0.00 0.00 0.00 ns t he enable input hold 0.00 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 0.38 ns t cpwlh clock pulse width low to high 0.39 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 0.37 ns t reasyn asynchronous recovery time 0.13 0.15 0.17 ns t hasyn asynchronous removal time 0.00 0.00 0.00 ns t clr asynchronous clear-to-q 0.23 0.27 0.31 ns t preset asynchronous preset-to-q 0.23 0.27 0.31 ns table 2-22 ? 3.3 v lvttl i/o module worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c (continued) ?2 speed ?1 speed std speed parameter description min. max. min. max. min. max. units
detailed specifications 2-28 revision 18 lvttl output drive strength =3 (16 ma) / low slew rate t dp input buffer 1.68 1.92 2.26 ns t py output buffer 11.03 12.56 14.77 ns t enzl enable to pad delay through the output buffer?z to low 11.42 13.01 15.29 ns t enzh enable to pad delay through the output buffer?z to high 11.04 12.58 14.79 ns t enlz enable to pad delay through the output buffer?low to z 1.86 1.88 1.88 ns t enhz enable to pad delay through the output buffer?high to z 2.50 2.51 2.52 ns t ioclkq sequential clock-to-q for the i/ o input register 0.67 0.77 0.90 ns t ioclky clock-to-output y for the i/o output register and the i/o enable register 0.67 0.77 0.90 ns t sud data input set-up 0.23 0.27 0.31 ns t sue enable input set-up 0.26 0.30 0.35 ns t hd data input hold 0.00 0.00 0.00 ns t he enable input hold 0.00 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 0.37 ns t reasyn asynchronous recovery time 0.13 0.15 0.17 ns t hasyn asynchronous removal time 0.00 0.00 0.00 ns t clr asynchronous clear-to-q 0.23 0.27 0.31 ns t preset asynchronous preset-to-q 0.23 0.27 0.31 ns table 2-22 ? 3.3 v lvttl i/o module worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c (continued) ?2 speed ?1 speed std speed parameter description min. max. min. max. min. max. units
axcelerator family fpgas revision 18 2-29 lvttl output drive strength = 4 (24 ma) / low slew rate t dp input buffer 1.68 1.92 2.26 ns t py output buffer 10.45 11.90 13.99 ns t enzl enable to pad delay through the output buffer?z to low 10.61 12.08 14.21 ns t enzh enable to pad delay through the output buffer?z to high 10.47 11.93 14.02 ns t enlz enable to pad delay through the output buffer?low to z 1.92 1.94 1.94 ns t enhz enable to pad delay through the output buffer?high to z 2.57 2.58 2.59 ns t ioclkq sequential clock-to-q for the i/ o input register 0.67 0.77 0.90 ns t ioclky clock-to-output y for the i/o output register and the i/o enable register 0.67 0.77 0.90 ns t sud data input set-up 0.23 0.27 0.31 ns t sue enable input set-up 0.26 0.30 0.35 ns t hd data input hold 0.00 0.00 0.00 ns t he enable input hold 0.00 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 0.37 ns t reasyn asynchronous recovery time 0.13 0.15 0.17 ns t hasyn asynchronous removal time 0.00 0.00 0.00 ns t clr asynchronous clear-to-q 0.23 0.27 0.31 ns t preset asynchronous preset-to-q 0.23 0.27 0.31 ns table 2-22 ? 3.3 v lvttl i/o module worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c (continued) ?2 speed ?1 speed std speed parameter description min. max. min. max. min. max. units
detailed specifications 2-30 revision 18 lvttl output drive strength = 1 (8 ma) / high slew rate t dp input buffer 1.68 1.92 2.26 ns t py output buffer 4.23 4.81 5.66 ns t enzl enable to pad delay through the output buffer?z to low 4.64 5.28 6.21 ns t enzh enable to pad delay through the output buffer?z to high 4.23 4.81 5.66 ns t enlz enable to pad delay through the output buffer?low to z 1.89 1.91 1.91 ns t enhz enable to pad delay through the output buffer?high to z 2.01 2.02 2.03 ns t ioclkq sequential clock-to-q for the i/ o input register 0.67 0.77 0.90 ns t ioclky clock-to-output y for the i/o output register and the i/o enable register 0.67 0.77 0.90 ns t sud data input set-up 0.23 0.27 0.31 ns t sue enable input set-up 0.26 0.30 0.35 ns t hd data input hold 0.00 0.00 0.00 ns t he enable input hold 0.00 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 0.37 ns t reasyn asynchronous recovery time 0.13 0.15 0.17 ns t hasyn asynchronous removal time 0.00 0.00 0.00 ns t clr asynchronous clear-to-q 0.23 0.27 0.31 ns t preset asynchronous preset-to-q 0.23 0.27 0.31 ns table 2-22 ? 3.3 v lvttl i/o module worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c (continued) ?2 speed ?1 speed std speed parameter description min. max. min. max. min. max. units
axcelerator family fpgas revision 18 2-31 lvttl output drive strength = 2 (12 ma) / high slew rate t dp input buffer 1.68 1.92 2.26 ns t py output buffer 3.30 3.76 4.42 ns t enzl enable to pad delay through the output buffer?z to low 3.74 4.26 5.00 ns t enzh enable to pad delay through the output buffer?z to high 3.06 3.49 4.10 ns t enlz enable to pad delay through the output buffer?low to z 1.89 1.91 1.91 ns t enhz enable to pad delay through the output buffer?high to z 2.29 2.30 2.31 ns t ioclkq sequential clock-to-q for the i/ o input register 0.67 0.77 0.90 ns t ioclky clock-to-output y for the i/o output register and the i/o enable register 0.67 0.77 0.90 ns t sud data input set-up 0.23 0.27 0.31 ns t sue enable input set-up 0.26 0.30 0.35 ns t hd data input hold 0.00 0.00 0.00 ns t he enable input hold 0.00 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 0.37 ns t reasyn asynchronous recovery time 0.13 0.15 0.17 ns t hasyn asynchronous removal time 0.00 0.00 0.00 ns t clr asynchronous clear-to-q 0.23 0.27 0.31 ns t preset asynchronous preset-to-q 0.23 0.27 0.31 ns table 2-22 ? 3.3 v lvttl i/o module worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c (continued) ?2 speed ?1 speed std speed parameter description min. max. min. max. min. max. units
detailed specifications 2-32 revision 18 lvttl output drive strength =3 (16 ma) / high slew rate t dp input buffer 1.68 1.92 2.26 ns t py output buffer 3.12 3.56 4.18 ns t enzl enable to pad delay through the output buffer?z to low 3.54 4.04 4.75 ns t enzh enable to pad delay through the output buffer?z to high 2.78 3.17 3.72 ns t enlz enable to pad delay through the output buffer?low to z 1.91 1.93 1.93 ns t enhz enable to pad delay through the output buffer?high to z 2.58 2.59 2.60 ns t ioclkq sequential clock-to-q for the i/ o input register 0.67 0.77 0.90 ns t ioclky clock-to-output y for the i/o output register and the i/o enable register 0.67 0.77 0.90 ns t sud data input set-up 0.23 0.27 0.31 ns t sue enable input set-up 0.26 0.30 0.35 ns t hd data input hold 0.00 0.00 0.00 ns t he enable input hold 0.00 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 0.37 ns t reasyn asynchronous recovery time 0.13 0.15 0.17 ns t hasyn asynchronous removal time 0.00 0.00 0.00 ns t clr asynchronous clear-to-q 0.23 0.27 0.31 ns t preset asynchronous preset-to-q 0.23 0.27 0.31 ns table 2-22 ? 3.3 v lvttl i/o module worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c (continued) ?2 speed ?1 speed std speed parameter description min. max. min. max. min. max. units
axcelerator family fpgas revision 18 2-33 lvttl output drive strength = 4 (24ma) / high slew rate t dp input buffer 1.68 1.92 2.26 ns t py output buffer 2.99 3.41 4.01 ns t enzl enable to pad delay through the output buffer?z to low 2.49 2.51 2.51 ns t enzh enable to pad delay through the output buffer?z to high 2.59 2.95 3.46 ns t enlz enable to pad delay through the output buffer?low to z 1.91 1.93 1.93 ns t enhz enable to pad delay through the output buffer?high to z 3.56 4.06 4.77 ns t ioclkq sequential clock-to-q for the i/ o input register 0.67 0.77 0.90 ns t ioclky clock-to-output y for the i/o output register and the i/o enable register 0.67 0.77 0.90 ns t sud data input set-up 0.23 0.27 0.31 ns t sue enable input set-up 0.26 0.30 0.35 ns t hd data input hold 0.00 0.00 0.00 ns t he enable input hold 0.00 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 0.37 ns t reasyn asynchronous recovery time 0.13 0.15 0.17 ns t hasyn asynchronous removal time 0.00 0.00 0.00 ns t clr asynchronous clear-to-q 0.23 0.27 0.31 ns t preset asynchronous preset-to-q 0.23 0.27 0.31 ns table 2-22 ? 3.3 v lvttl i/o module worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c (continued) ?2 speed ?1 speed std speed parameter description min. max. min. max. min. max. units
detailed specifications 2-34 revision 18 2.5 v lvcmos low-voltage complementary metal-oxide semiconduc tor for 2.5 v is an extension of the lvcmos standard (jesd8-5) used for general-purpose 2.5 v applications. it uses a 3. 3 v tolerant cmos input buffer and a push-pull output buffer. ac loadings table 2-23 ? dc input and output levels vil vih vol voh iol ioh min., v max., v min., v max., v max., v min., v ma ma -0.3 0.7 1.7 3.6 0.4 2.0 12 ?12 figure 2-16 ? ac test loads table 2-24 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measur ing point* (v) vref (typ) (v) c load (pf) 0 2.5 1.25 n/a 35 note: * measuring point = vtrip r to v cci for t plz / t pzl r to gnd for t phz / t pzh 35 pf for t pzh / t pzl 5 pf for t phz / t plz test point test point 35 pf for tristate r=1k for t pd
axcelerator family fpgas revision 18 2-35 timing characteristics table 2-25 ? 2.5v lvcmos i/o module worst-case commercial conditions vcca = 1.425 v, vcci = 2.3 v, t j = 70c ?2 speed ?1 speed std speed parameter description min. max. min. max. min. max. units lvcmos25 i/o module timing t dp input buffer 1.95 2.22 2.61 ns t py output buffer 3.29 3.74 4.40 ns t enzl enable to pad delay through the output buffer?z to low 2.48 2.50 2.51 ns t enzh enable to pad delay through the output buffer?z to high 2.48 2.50 2.51 ns t enlz enable to pad delay through the output buffer?low to z 5.74 6.54 7.69 ns t enhz enable to pad delay through the output buffer?high to z 6.60 7.51 8.83 ns t ioclkq sequential clock-to-q for the i/o input register 0.67 0.77 0.90 ns t ioclky clock-to-output y for the i/o output register and the i/o enable register 0.67 0.77 0.90 ns t sud data input set-up 0.23 0.27 0.31 ns t sue enable input set-up 0.26 0.30 0.35 ns t hd data input hold 0.00 0.00 0.00 ns t he enable input hold 0.00 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 0.37 ns t reasyn asynchronous recovery time 0.13 0.15 0.17 ns t hasyn asynchronous removal time 0.00 0.00 0.00 ns t clr asynchronous clear-to-q 0.23 0.27 0.31 ns t preset asynchronous preset-to-q 0.23 0.27 0.31 ns
detailed specifications 2-36 revision 18 1.8 v lvcmos low-voltage complementary metal-oxide semiconduc tor for 1.8 v is an extension of the lvcmos standard (jesd8-5) used for general-purpose 1.8 v applications. it uses a 3. 3 v tolerant cmos input buffer and a push-pull output buffer. ac loadings table 2-26 ? dc input and output levels vil vih vol voh iol ioh min., v max., v min., v max., v max., v min., v ma ma ?0.3 0.2 vcci 0.7 vcci 3.6 0.2 vcci ? 0.2 8 ma ?8 ma figure 2-17 ? ac test loads table 2-27 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measu ring point* (v) vref (typ) (v) c load (pf) 0 1.8 0.5 vcci n/a 35 note: * measuring point = vtrip r to v cci for t plz / t pzl r to gnd for t phz / t pzh 35 pf for t pzh / t pzl 5 pf for t phz / t plz test point test point 35 pf for tristate r=1k for t pd
axcelerator family fpgas revision 18 2-37 timing characteristics table 2-28 ? 1.8v lvcmos i/o module worst-case commercial conditions vcca = 1.425 v, vcci = 1.7 v, tj = 70c ?2 speed ?1 speed std speed parameter description min. max. min. max. min. max. units lvcmos18 output module timing t dp input buffer 3.26 3.71 4.37 ns t py output buffer 4.55 5.18 6.09 ns t enzl enable to pad delay through the output buffer?z to low 2.82 2.83 2.84 ns t enzh enable to pad delay through the output buffer?z to high 3.43 3.45 3.46 ns t enlz enable to pad delay through the output buffer?low to z 6.01 6.85 8.05 ns t enhz enable to pad delay through the output buffer?high to z 6.73 7.67 9.01 ns t ioclkq sequential clock-to-q for the i/o input register 0.67 0.77 0.90 ns t ioclky clock-to-output y for the i/o output register and the i/o enable register 0.67 0.77 0.90 ns t sud data input set-up 0.23 0.27 0.31 ns t sue enable input set-up 0.26 0.30 0.35 ns t hd data input hold 0.00 0.00 0.00 ns t he enable input hold 0.00 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 0.37 ns t reasyn asynchronous recovery time 0.13 0.15 0.17 ns t hasyn asynchronous removal time 0.00 0.00 0.00 ns t clr asynchronous clear-to-q 0.23 0.27 0.31 ns t preset asynchronous preset-to-q 0.23 0.27 0.31 ns
detailed specifications 2-38 revision 18 1.5 v lvcmos (jesd8-11) low-voltage complementary metal-oxide semiconduc tor for 1.5 v is an extension of the lvcmos standard (jesd8-5) used for general-purpose 1.5 v applications. it uses a 3. 3 v tolerant cmos input buffer and a push-pull output buffer. ac loadings table 2-29 ? dc input and output levels vil vih vol voh iol ioh min., v max., v min., v max., v max., v min., v ma ma ?0.3 0.35 vcci 0.65 vcci 3.6 0.4 vcci ? 0.4 8 ma ?8 ma table 2-30 ? ac test loads table 2-31 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measu ring point* (v) vref (typ) (v) c load (pf) 0 1.5 0.5v cci n/a 35 note: * measuring point = vtrip r to v cci for t plz / t pzl r to gnd for t phz / t pzh 35 pf for t pzh / t pzl 5 pf for t phz / t plz test point test point 35 pf for tristate r=1k for t pd
axcelerator family fpgas revision 18 2-39 timing characteristics table 2-32 ? 1.5v lvcmos i/o module worst-case commercial conditions vcca = 1.425 v, vcci = 1.4 v, tj = 70c ?2 speed ?1 speed std speed parameter description min. max. min. max. min. max. units lvcmos15 (jesd8-11) i/o module timing t dp input buffer 3.59 4.09 4.81 ns t py output buffer 6.05 6.89 8.10 ns t enzl enable to pad delay through the output buffer?z to low 3.31 3.34 3.34 ns t enzh enable to pad delay through the output buffer?z to high 4.56 4.58 4.59 ns t enlz enable to pad delay through the output buffer?low to z 6.37 7.25 8.52 ns t enhz enable to pad delay through the output buffer?high to z 6.94 7.90 9.29 ns t ioclkq sequential clock-to-q for the i/o input register 0.67 0.77 0.90 ns t ioclky clock-to-output y for the i/o output register and the i/o enable register 0.67 0.77 0.90 ns t sud data input set-up 0.23 0.27 0.31 ns t sue enable input set-up 0.26 0.30 0.35 ns t hd data input hold 0.00 0.00 0.00 ns t he enable input hold 0.00 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 0.37 ns t reasyn asynchronous recovery time 0.13 0.15 0.17 ns t hasyn asynchronous removal time 0.00 0.00 0.00 ns t clr asynchronous clear-to-q 0.23 0.27 0.31 ns t preset asynchronous preset-to-q 0.23 0.27 0.31 ns
detailed specifications 2-40 revision 18 3.3 v pci, 3.3 v pci-x peripheral component interface for 3.3 v standard specifies support for both 33 mhz and 66 mhz pci bus applications. it uses an lvttl input buffer and a push-pull output buffer. the input and output buffers are 5 v tolerant with the aid of external components. axcelerator 3.3 v pci and 3.3 v pci-x buffers are compliant with the pci local bus specification rev. 2.1. the pci compliance specification re quires the clamp diodes to be able to withstand for 11 ns, ?3.5 v in undershoot, and 7.1 v in overshoot. ac loadings table 2-33 ? dc input and output levels vil vih vol voh iol ioh min., v max., v min., v max., v max., v min., v ma ma pci ?0.3 0.3 vcci 0.5 vcci vcci + 0.5 (per pci specification) pci-x ?0.5 0.35 vcci 0.5 vcci vcci + 0.5 (per pci specification) figure 2-18 ? ac test loads table 2-34 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measu ring point* (v) vref (typ) (v) c load (pf) (per pci spec and pci-x spec) n/a 10 note: * measuring point = vtrip r to vcci for t pl r to gnd for t ph 10 pf gnd test point for data r = 25 35 pf for t pzl / t pzh 5 pf for t phz / t plz r to v cci for t plz / t pzl r to gnd for t phz / t pzh test point for tristate r = 1k
axcelerator family fpgas revision 18 2-41 timing characteristics table 2-35 ? 3.3 v pci i/o module worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed units parameter description min. max. min. max. min. max. 3.3 v pci output module timing t dp input buffer 1.57 1.79 2.10 ns t py output buffer 1.91 2.18 2.56 ns t enzl enable to pad delay through the output buffer?z to low 1.61 1.62 1.63 ns t enzh enable to pad delay through the output buffer?z to high 1.45 1.47 1.47 ns t enlz enable to pad delay through the output buffer?low to z 2.55 2.90 3.41 ns t enhz enable to pad delay through the output buffer?high to z 3.52 4.01 4.72 ns t ioclkq sequential clock-to-q for the i/o input register 0.67 0.77 0.90 ns t ioclky clock-to-output y for the i/o output register and the i/o enable register 0.67 0.77 0.90 ns t sud data input set-up 0.23 0.27 0.31 ns t sue enable input set-up 0.26 0.30 0.35 ns t hd data input hold 0.00 0.00 0.00 ns t he enable input hold 0.00 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 0.37 ns t reasyn asynchronous recovery time 0.13 0.15 0.17 ns t hasyn asynchronous removal time 0.00 0.00 0.00 ns t clr asynchronous clear-to-q 0.23 0.27 0.31 t preset asynchronous preset-to-q 0.23 0.27 0.31 ns
detailed specifications 2-42 revision 18 table 2-36 ? 3.3 v pci-x i/o module worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed units parameter description min. max. min. max. min. max. 3.3 v pci-x output module timing t dp input buffer 1.57 1.79 2.10 ns t py output buffer 2.10 2.40 2.82 ns t enzl enable to pad delay through the output buffer?z to low 1.61 1.62 1.63 ns t enzh enable to pad delay through the output buffer?z to high 1.59 1.60 1.61 ns t enlz enable to pad delay through the output buffer?low to z 2.65 3.02 3.55 ns t enhz enable to pad delay through the output buffer?high to z 3.11 3.55 4.17 ns t ioclkq sequential clock-to-q for the i/o input register 0.67 0.77 0.90 ns t ioclky clock-to-output y for the i/o output register and the i/o enable register 0.67 0.77 0.90 ns t sud data input set-up 0.23 0.27 0.31 ns t sue enable input set-up 0.26 0.30 0.35 ns t hd data input hold 0.00 0.00 0.00 ns t he enable input hold 0.00 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 0.37 ns t reasyn asynchronous recovery time 0.13 0.15 0.17 ns t hasyn asynchronous removal time 0.00 0.00 0.00 ns t clr asynchronous clear-to-q 0.23 0.27 0.31 ns t preset asynchronous preset-to-q 0.23 0.27 0.31 ns
axcelerator family fpgas revision 18 2-43 voltage-referenced i/o standards gtl+ gunning transceiver logic plus is a high-speed bu s standard (jesd8-3). it requires a differential amplifier input buffer and an open drain output buffer . the vcci pin should be connected to 2.5 v or 3.3 v. note that 2.5 v gtl+ is not suppor ted across the full milit ary temperature range. ac loadings timing characteristics table 2-37 ? dc input and output levels vil vih vol voh iol ioh min., v max., v min., v max., v max., v min., v ma ma n/a vref ? 0.1 vref + 0.1 n/a 0.6 na na na figure 2-19 ? ac test loads table 2-38 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measu ring point* (v) vref (typ) (v) c load (pf) vref ? 0.2 vref + 0.2 vref 1.0 10 note: * measuring point = vtrip test point 10 pf 25 vtt table 2-39 ? 2.5 v gtl+ i/o module worst-case commercial conditions vcca = 1.425 v, vcci = 2.3 v, t j = 70c ?2 speed ?1 speed std speed units parameter description mi n. max. min. max. min. max. 2.5 v gtl+ i/o module timing t dp input buffer 1.71 1.95 2.29 ns t py output buffer 1.13 1.29 1.52 ns t iclkq clock-to-q for the i/o input register 0.67 0.77 0.90 ns t oclkq clock-to-q for the i/o output register and the i/o enable register 0.67 0.77 0.90 ns t sud data input set-up 0.23 0.27 0.31 ns t sue enable input set-up 0.26 0.30 0.35 ns t hd data input hold 0.00 0.00 0.00 ns t he enable input hold 0.00 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 0.37 ns t reasyn asynchronous recovery time 0.13 0.15 0.17 ns t hasyn asynchronous removal time 0.00 0.00 0.00 ns t clr asynchronous clear-to-q 0.23 0.27 0.31 ns t preset asynchronous preset-to-q 0.23 0.27 0.31 ns
detailed specifications 2-44 revision 18 table 2-40 ? 3.3 v gtl+ i/o module worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed units parameter description min. max. min. max. min. max. 3.3 v gtl+i/o module timing t dp input buffer 1.71 1.95 2.29 ns t py output buffer 1.13 1.29 1.52 ns t iclkq clock-to-q for the i/o input register 0.67 0.77 0.90 ns t oclkq clock-to-q for the i/o output register and the i/o enable register 0.67 0.77 0.90 ns t sud data input set-up 0.23 0.27 0.31 ns t sue enable input set-up 0.26 0.30 0.35 ns t hd data input hold 0.00 0.00 0.00 ns t he enable input hold 0.00 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 0.37 ns t reasyn asynchronous recovery time 0.13 0.15 0.17 ns t hasyn asynchronous removal time 0.00 0.00 0.00 ns t clr asynchronous clear-to-q 0.23 0.27 0.31 ns t preset asynchronous preset-to-q 0.23 0.27 0.31 ns
axcelerator family fpgas revision 18 2-45 hstl class i high-speed transceiver logic is a general-purpose high-speed 1.5 v bus standard (eia/jesd8-6). the axcelerator devices support class i. this requires a differential amplifier input buffer and a push-pull output buffer. ac loadings timing characteristics table 2-41 ? dc input and output levels vil vih vol voh iol ioh min., v max., v min., v max., v max., v min., v ma ma -0.3 vref ? 0.1 vref + 0.1 3.6 0.4 vcc ? 0.4 8 -8 figure 2-20 ? ac test loads table 2-42 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) meas uring point* (v) vref (typ) (v) c load (pf) vref ?0.5 vref + 0.5 vref 0.75 20 note: * measuring point = vtrip test point 20 pf 50 vtt table 2-43 ? 1.5 v hstl class i i/o module worst-case commercial conditions v cca = 1.425 v, vcci = 1.425 v, t j = 70c ?2 speed ?1 speed std speed units parameter description min . max. min. max. min. max. 1.5 v hstl class i i/o module timing t dp input buffer 1.80 2.05 2.41 ns t py output buffer 4.90 5.58 6.56 ns t iclkq clock-to-q for the i/o inpu t register 0.67 0.77 0.90 ns t oclkq clock-to-q for the i/o output register and the i/o enable register 0.67 0.77 0.90 ns t sud data input set-up 0.23 0.27 0.31 ns t sue enable input set-up 0.26 0.30 0.35 ns t hd data input hold 0.00 0.00 0.00 ns t he enable input hold 0.00 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 0.37 ns t reasyn asynchronous recovery time 0.13 0.15 0.17 ns t hasyn asynchronous removal time 0.00 0.00 0.00 ns t clr asynchronous clear-to-q 0.23 0.27 0.31 ns t preset asynchronous preset-to-q 0.23 0.27 0.31 ns
detailed specifications 2-46 revision 18 sstl2 stub series terminated logic for 2.5 v is a gener al-purpose 2.5 v memory bus standard (jesd8-9). the axcelerator devices support both classes of this standard. this requires a differential amplifier input buffer and a push-pull output buffer. class i ac loadings timing characteristics table 2-44 ? dc input and output levels vil vih vol voh iol ioh min., v max., v min., v max., v max., v min., v ma ma ?0.3 vref ? 0.2 vref + 0.2 3.6 vref ? 0.57 vref + 0.57 7.6 ?7.6 figure 2-21 ? ac test loads table 2-45 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) meas uring point* (v) vref (typ) (v) c load (pf) vref ? 0.75 vref + 0.75 vref 1.25 30 note: * measuring point = vtrip test point 30 pf 50 25 vtt table 2-46 ? 2.5 v sstl2 class i i/o module worst-case commercial conditions vcca = 1.425 v, vcci = 2.3 v, t j = 70c ?2 speed ?1 speed std speed parameter description min. max. min. max. min. max. units 2.5 v sstl2 class i i/o module timing t dp input buffer 1.83 2.08 2.45 ns t py output buffer 2.39 2.72 3.20 ns t iclkq clock-to-q for the i/o input register 0.67 0.77 0.90 ns t oclkq clock-to-q for the i/o output register and the i/o enable register 0.67 0.77 0.90 ns t sud data input set-up 0.23 0.27 0.31 ns t sue enable input set-up 0.26 0.30 0.35 ns t hd data input hold 0.00 0.00 0.00 ns t he enable input hold 0.00 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 0.37 ns t reasyn asynchronous recovery time 0.13 0.15 0.17 ns t hasyn asynchronous removal time 0.00 0.00 0.00 ns t clr asynchronous clear-to-q 0.23 0.27 0.31 ns t preset asynchronous preset-to-q 0.23 0.27 0.31 ns
axcelerator family fpgas revision 18 2-47 class ii ac loadings timing characteristics table 2-47 ? dc input and output levels vil vih vol voh iol ioh min., v max., v min., v max., v max., v min,. v ma ma -0.3 vref ? 0.2 vref + 0.2 3.6 vref ? 0.8 vref + 0.8 15.2 -15.2 figure 2-22 ? ac test loads table 2-48 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) vref (typ) (v) c load (pf) vref ? 0.75 vref + 0.75 vref 1.25 30 note: * measuring point = v trip test point 30 pf 25 25 v tt table 2-49 ? 2.5 v sstl2 class ii i/o module worst-case commercial conditions vcca = 1.425 v, vcci = 2.3 v, t j = 70c ?2 speed ?1 speed std speed units parameter description mi n. max. min. max. min. max. 2.5 v sstl2 class ii i/o module timing t dp input buffer 1.89 2.16 2.53 ns t py output buffer 2.39 2.72 3.20 ns t iclkq clock-to-q for the i/o input register 0.67 0.77 0.90 ns t oclkq clock-to-q for the i/o output register and the i/o enable register 0.67 0.77 0.90 ns t sud data input set-up 0.23 0.27 0.31 ns t sue enable input set-up 0.26 0.30 0.35 ns t hd data input hold 0.00 0.00 0.00 ns t he enable input hold 0.00 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 0.37 ns t reasyn asynchronous recovery time 0.13 0.15 0.17 ns t hasyn asynchronous removal time 0.00 0.00 0.00 ns t clr asynchronous clear-to-q 0.23 0.27 0.31 ns t preset asynchronous preset-to-q 0.23 0.27 0.31 ns
detailed specifications 2-48 revision 18 sstl3 stub series terminated logic for 3.3 v is a gener al-purpose 3.3 v memory bus standard (jesd8-8). the axcelerator devices support both classes of this standard. this requires a differential amplifier input buffer and a push-pull output buffer. class i ac loadings timing characteristics table 2-50 ? dc input and output levels vil vih vol voh iol ioh min., v max., v min., v max., v max., v min., v ma ma -0.3 vref ? 0.2 vref +0.2 3.6 vref ? 0.6 vref + 0.6 8 ?8 figure 2-23 ? ac test loads table 2-51 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measu ring point* (v) vref (typ) (v) c load (pf) vref ? 1.0 vref + 1.0 vref 1.50 30 note: *measuring point = vtrip test point 30 pf 50 25 vtt table 2-52 ? 3.3 v sstl3 class i i/o module worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed parameter description min. ma x. min. max. min. max. units 3.3 v sstl3 class i i/o module timing t dp input buffer 1.78 2.03 2.39 ns t py output buffer 2.17 2.47 2.91 ns t iclkq clock-to-q for the i/o input register 0.67 0.77 0.90 ns t oclkq clock-to-q for the i/o output register and the i/o enable register 0.67 0.77 0.90 ns t sud data input set-up 0.23 0.27 0.31 ns t sue enable input set-up 0.26 0.30 0.35 ns t hd data input hold 0.00 0.00 0.00 ns t he enable input hold 0.00 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 0.37 ns t reasyn asynchronous recovery time 0.13 0.15 0.17 ns t hasyn asynchronous removal time 0.00 0.00 0.00 ns t clr asynchronous clear-t o-q 0.23 0.27 0.31 ns t preset asynchronous preset-to-q 0.23 0.27 0.31 ns
axcelerator family fpgas revision 18 2-49 class ii ac loadings timing characteristics table 2-53 ? dc input and output levels vil vih vol voh iol ioh min., v max., v min., v max., v max., v min., v ma ma -0.3 vref ? 0.2 vref + 0.2 3.6 vref ? 0.8 vref + 0.8 16 ?16 figure 2-24 ? ac test loads table 2-54 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measu ring point* (v) vref (typ) (v) c load (pf) vref ? 1.0 vref + 1.0 vref 1.50 30 note: * measuring point = vtrip test point 30 pf 25 25 v tt table 2-55 ? 3.3 v sstl3 class ii i/o module worst-case commercial conditions vcca = 1.425 v, vcci = 3.0v, t j = 70c ?2 speed ?1 speed std speed parameter description min. max. min. max. min. max. units 3.3 v sstl3 class ii i/o module timing t dp input buffer 1.85 2.10 2.47 ns t py output buffer 2.17 2.47 2.91 ns t iclkq clock-to-q for the i/o i nput register 0.67 0.77 0.90 ns t oclkq clock-to-q for the i/o output register and the i/o enable register 0.67 0.77 0.90 ns t sud data input set-up 0.23 0.27 0.31 ns t sue enable input set-up 0.26 0.30 0.35 ns t hd data input hold 0.00 0.00 0.00 ns t he enable input hold 0.00 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 0.37 ns t reasyn asynchronous recovery time 0.13 0.15 0.17 ns t hasyn asynchronous removal time 0.00 0.00 0.00 ns t clr asynchronous clear-to-q 0.23 0.27 0.31 ns t preset asynchronous preset-to-q 0.23 0.27 0.31 ns
detailed specifications 2-50 revision 18 differential standards physical implementation implementing differential i/o standards requires the config uration of a pair of external i/o pads, resulting in a single internal signal. to facilitate construction of the differential pair, a single i/o cluster contains the resources for a pair of i/os. confi guration of the i/o cluster as a diff erential pair is handled by designer software when the user instantiates a differential i/o macro in the design. differential i/os can also be used in conjuncti on with the embedded input r egister (inreg), output register (outreg), enable register (enreg), an d double data rate (ddr). however, there is no support for bidirectional i/os or tristates with these standards. lvds low-voltage differential signal (ans i/tia/eia-644) is a hi gh-speed, differential i/o standard. it requires that one data bit is carried through two signal lines, so two pins are needed. it also requires an external resistor termination. the voltage swing between these two signal lines is approximately 350 mv. the lvds circuit consists of a differential driver connected to a terminated receiver through a constant- impedance transmission line. the receiver is a wide-common-mode-range differential amplifier. the common-mode range is from 0.2 v to 2.2 v for a differential input with 400 mv swing. to implement the driver for the lvds circuit, driver s from two adjacent i/o cells are used to generate the differential signals (note that the driver is not a current-mode drive r). this driver provides a nominal constant current of 3.5 ma. when this current flows through a 100 termination resistor on the receiver side, a voltage swing of 350 mv is developed across the resistor. the direction of the current flow is controlled by the data fed to the driver. an external-resistor network (three resistors) is needed to reduce the voltage swing to about 350 mv. therefore, four external resistors are required, three for the driver and one for the receiver. figure 2-25 ? lvds board-level implementation 140 100 zo = 50 zo = 50 165 165 + ? p n p n inbuf_lvds outbuf_lvds fpga fpga table 2-56 ? dc input and output levels dc parameter description min. typ. max. units vcci 1 supply voltage 2.375 2.5 2.625 v voh output high voltage 1.25 1.425 1.6 v vol output low voltage 0.9 1.075 1.25 v vodiff differential output voltage 250 350 450 mv vocm output common mode voltage 1.125 1.25 1.375 v vicm2 input common mode voltage 0.2 1.25 2.2 v notes: 1. 5% 2. differential input voltage = 350 mv.
axcelerator family fpgas revision 18 2-51 timing characteristics table 2-57 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) 1.2 ? 0.125 1. 2 + 0.125 1.2 note: * measuring point = vtrip table 2-58 ? lvds i/o module worst-case commercial conditions vcca = 1.425 v, vcci = 2.3 v, t j = 70c ?2 speed ?1 speed std speed units parameter description min. max. min. max. min. max. lvds output module timing t dp input buffer 1.80 2.05 2.41 ns t py output buffer 2.32 2.64 3.11 ns t iclkq clock-to-q for the i/o i nput register 0. 67 0.77 0.90 ns t oclkq clock-to-q for the i/ o output register and the i/o enable register 0.67 0.77 0.90 ns t sud data input set-up 0.23 0.27 0.31 ns t sue enable input set-up 0.26 0.30 0.35 ns t hd data input hold 0.00 0.00 0.00 ns t he enable input hold 0.00 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 0.37 ns t reasyn asynchronous recovery time 0.13 0.15 0.17 ns t hasyn asynchronous removal time 0.00 0.00 0.00 ns t clr asynchronous clear-to-q 0.23 0.27 0.31 ns t preset asynchronous preset-to-q 0.23 0.27 0.31 ns
detailed specifications 2-52 revision 18 lvpecl low-voltage positive emitter-coupled logic (lvpecl) is another differ ential i/o standard. it requires that one data bit is carried through two signal lines . like lvds, two pins are needed. it also requires external resistor termination. the voltage swing between these two signal lines is approximately 850 mv. the lvpecl circuit is similar to the lvds scheme. it re quires four external resist ors, three for the driver and one for the receiver. the values for the three driver resistors are different from that of lvds since the output voltage levels are different. please note th at the voh levels are 200 mv below the standard lvpecl levels. figure 2-26 ? lvpecl board-level implementation 187 100 zo = 50 zo = 50 100 100 + ? p n p n inbuf_lvpecl outbuf_lvpecl fpga fpga table 2-59 ? dc input and output levels dc parameter min. typ. max. units min. max. min. max. min. max. vcci 3 3.3 3.6 v voh 1.8 2.11 1.92 2.28 2.13 2.41 v vol 0.96 1.27 1.06 1.43 1.3 1.57 v vih 1.49 2.72 1.49 2.72 1.49 2.72 v vil 0.86 2.125 0.86 2.125 0.86 2.125 v differential input voltage 0.3 0.3 0.3 v table 2-60 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) 1.6 ? 0.3 1.6 + 0.3 1.6 note: * measuring point = vtrip
axcelerator family fpgas revision 18 2-53 timing characteristics table 2-61 ? lvpecl i/o module worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed parameter description min. ma x. min. max. min. max. units lvpecl output module timing t dp input buffer 1.66 1.89 2.22 ns t py output buffer 2.24 2.55 3.00 ns t iclkq clock-to-q for the i/o i nput register 0.67 0.77 0.90 ns t oclkq clock-to-q for the io output register and the i/o enable register 0.67 0.77 0.90 ns t sud data input set-up 0.23 0.27 0.31 ns t sue enable input set-up 0.26 0.30 0.35 ns t hd data input hold 0.00 0.00 0.00 ns t he enable input hold 0.00 0.00 0.00 ns t cpwhl clock pulse width high to low 0.39 0.39 0.39 ns t cpwlh clock pulse width low to high 0.39 0.39 0.39 ns t wasyn asynchronous pulse width 0.37 0.37 0.37 ns t reasyn asynchronous recovery time 0.13 0.15 0.17 ns t hasyn asynchronous removal time 0.00 0.00 0.00 ns t clr asynchronous clear-to-q 0.23 0.27 0.31 ns t preset asynchronous preset-to-q 0.23 0.27 0.31 ns
detailed specifications 2-54 revision 18 module specifications c-cell introduction the c-cell is one of the two logic module types in the ax architecture. it is the combinatorial logic resource in the axcelerator device. the ax architectu re implements a new combinatorial cell that is an extension of the c-cell implemente d in the sx-a family. the main enhancement of the new c-cell is the addition of carry-chain logic. the c-cell can be used in a carry-chain mode to construc t arithmetic functions. if carry-chain logic is not required, it can be disabled. the c-cell features the following ( figure 2-27 ): ? eight-input mux (data: d0-d3, select: a0, a1, b0, b1). user signals can be routed to any one of these inputs. any of the c-cell inputs (d0-d3, a0, a1, b0, b1) can be tied to one of the four routed clocks (clke/f/g/h). ? inverter (db input) can be used to drive a comple ment signal of any of the inputs to the c-cell. ? a carry input and a carry output. the carry input sig nal of the c-cell is the carry output from the c- cell directly to the north. ? carry connect for carry-chain logic with a signal propagation time of less than 0.1 ns. ? a hardwired connection (direct connect) to the adja cent r-cell (register cell) for all c-cells on the east side of a supercluster with a signal propagation time of less than 0.1 ns. this layout of the c-cell (and the c-cell cluster) enabl es the implementation of ov er 4,000 functions of up to five bits. for example, two c-cells can be used t ogether to implement a four-input xor function in a single cell delay. the carry-chain configuration is handled automatica lly for the user with microsemi's extensive macro library (please see the antifuse macro library guide for a complete listing of available axcelerator macros). figure 2-27 ? c-cell 1 0 d1 d3 b1 b0 d0 d2 db a1 a0 cfn fci fco y 0 0 0 0 1 1 1 1
axcelerator family fpgas revision 18 2-55 timing model and waveforms timing characteristics figure 2-28 ? c-cell timing model and waveforms y, fco y, fco gnd v cca 50% 50% 50% 50% gnd gnd 50% 50% a, b, d, fci t pd , t pdc v cca v cca t pd , t pdc t pd , t pdc t pd , t pdc table 2-62 ? c-cell worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed units parameter description min. max. min. max. min. max. c-cell propagation delays t pd any input to output y 0.74 0.84 0.99 ns t pdc any input to carry chain output (fco) 0.57 0.64 0.76 ns t pdb any input through db when one input is used 0.95 1.09 1.28 ns t ccy input to carry chain (f ci) to y 0.61 0.69 0.82 ns t cc input to carry chain (fci ) to carry chain output (fco) 0.08 0.09 0.11 ns
detailed specifications 2-56 revision 18 carry-chain logic the axcelerator dedicated carry-chain logic offers a very compact solution for implementing arithmetic functions without sacr ificing performance. to implement the carry-chain logic, two c-cells in a cluster are connected together so the fco (i.e. carry out) for the two bits is generated in a carry lo ok-ahead scheme to achieve minimum propagation delay from the fci (i.e. carry in) into the two-bit cluster. the two-bit carry logic is shown in figure 2-29 . the fci of one c-cell pair is driven by the fco of th e c-cell pair immediately above it. similarly, the fco of one c-cell pair, drives the fci input of the c-cell pair immediately below it ( figure 1-4 on page 1-3 and figure 2-30 on page 2-57 ). the carry-chain logic is selected via the cfn input. when carry logic is not required, this signal is deasserted to save power. again, this configuration is handled automatically for the user through microsemi's macro library. the signal propagation delay between two c-cells in the carry-chain sequence is 0.1 ns. figure 2-29 ? axcelerator?s two-bit carry logic 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 dcout d0 d2 db a1 a0 y fco y d0 d2 db a1 a0 d1 d3 b1 b0 d1 d3 b1 b0 cfn cfn fci
axcelerator family fpgas revision 18 2-57 timing characteristics refer to table 2-62 on page 2-55 for more information on carry-chain timing. note: the carry-chain sequence can end on either c-cell. figure 2-30 ? carry-chain sequencing of c-cells dcin dcout c-cell1 c-cell2 dcout r-cell1 dcin c-cell (2n-1) c-cell2n dcout r-celln cdin n-2 clusters fco 2n fci (2n-1) fci 5 fco 4 fci 3 fco 2 fci 1
detailed specifications 2-58 revision 18 r-cell introduction the r-cell, the sequential logic res ource of the axcelerator devices, is the second logic module type in the ax family architecture. it includes clock inputs for all eight global resources of the axcelerator architecture as well as global presets and clears ( figure 2-31 ). the main features of the r- cell include the following: ? direct connection to the adjacent logic modul e through the hardwired connection dcin. dcin is driven by the dcout of an adjac ent c-cell via the direct-connec t routing resource, providing a connection with less than 0. 1 ns of routing delay. ? the r-cell can be used as a standalone flip-flop. it can be driven by any c-cell or i/o modules through the regular routing structure (using din as a routable data input). this gives the option of using the r-cell as a 2:1 muxed flip-flop as well. ? provision of data enable-input (s0). ? independent active-low asynchronous clear (clr). ? independent active-low asynch ronous preset (pset). if bot h clr and pset are low, clr has higher priority. ? clock can be driven by any of the following (ckp selects clock polarity): ? one of the four high performanc e hardwired fast clocks (hclks) ? one of the four routed clocks (clks) ? user signals ? global power-on clear (gclr) and preset (gpset), which drive ea ch flip-flop on a chip-wide basis. ? when the global set fuse option in the designer software is unchecked (by default), gclr = 0 and gpset = 1 at device power-up. w hen the option is checked, gclr = 1 and gpset = 0. both pins are pulled high when the device is in user mode. refer to the "simulation support for gclr/gpset in axcelera tor" section of the antifuse macro library guide for information on simulation support for gclr and gpset. ? s0, s1, pset, and clr can be driven by routed clocks clke/f/g/h or user signals. ? din and s1 can be driven by user signals. as with the c-cell, the configuration of the r-cell to perform various functions is handled automatically for the user through microsemi's extensive macro library (see the antifuse macro library guide for a complete listing of available ax macros). figure 2-31 ? r-cell s1 s0 ckp clr gclr pset gpset dcin din(user signals) cks y hclka/b/c/d clke/f/g/h internal logic
axcelerator family fpgas revision 18 2-59 timing models and waveforms timing characteristics figure 2-32 ? r-cell delays e d q clr preset clk t sue t he t sud t hd t rco t wasyn t hasyn t clr t reasyn t cpwhl t cpwlh t preset t wasyn t hasyn t reasyn table 2-63 ? r-cell worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed units parameter description mi n. max. min. max. min. max. r-cell propagation delays t rco sequential clock-to-q 0.67 0.77 0.90 ns t clr asynchronous clear-to-q 0.67 0.77 0.90 ns t preset asynchronous preset-to-q 0.36 0.36 0.36 ns t sud flip-flop data input set-up 0.34 0.34 0.34 ns t sue flip-flop enable input set-up 0.00 0.00 0.00 ns t hd flip-flop data input hold 0.67 0.77 0.90 ns t he flip-flop enable input hold 0.67 0.77 0.90 ns t wasyn asynchronous pulse width 0.48 0.48 0.48 ns t reasyn asynchronous recovery time 0.23 0.27 0.31 ns t hasyn asynchronous removal time 0.36 0.36 0.36 ns t cpwhl clock pulse width high to low 0.36 0.36 0.36 ns t cpwlh clock pulse width low to high 0.36 0.36 0.36 ns
detailed specifications 2-60 revision 18 buffer module introduction an additional resource inside each super cluster is the buffer (b) module ( figure 1-4 on page 1-3 ). when a fanout constraint is applied to a design, the synthesis tool inserts buffers as needed. the buffer module has been added to the ax architecture to avoid logic duplication resulting from the hard fanout constraints. the router utilizes this logic resource to save area and reduce loading and delays on medium-to-high-fanout nets. timing models and waveforms timing characteristics figure 2-33 ? buffer module timing model figure 2-34 ? buffer module waveform table 2-64 ? buffer module worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed parameter description min. max. min. max. min. max. units buffer module propagation delays t bfpd any input to output y 0.12 0.14 0.16 ns in out out gnd 50% 50% 50% 50% gnd in vcca vcca t bfpd t bfpd
axcelerator family fpgas revision 18 2-61 routing specifications routing resources the routing structure found in axcelerator devices enables any logic module to be connected to any other logic module while retaining hi gh performance. there are multiple paths and routing resources that can be used to route one logic module to another, both within a supercluster and elsewhere on the chip. there are four primary types of routing within the ax architecture: directconnect, carryconnect, fastconnect, and vertical and horizontal routing. directconnect directconnects provide a high-speed connection be tween an r-cell and its adjacent c-cell ( figure 2-35 ). this connection can be made from dcout of the c-cell to dcin of th e r-cell by configuring of the s1 line of the r-cell. this provides a connection that does not require an antifuse and has a delay of less than 0.1 ns. carryconnect carryconnects are used to build carry chains for arithmetic functions ( figure 2-35 ). the fco output of the right c-cell of a two-c-cell cluster drives the fci input of the left c-cell in the two-c-cell cluster immediately below it. this pattern continues dow n both sides of each supercluster column. similar to the directconnects, carryconnects can be built without an antifuse connection. this connection has a delay of less than 0.1 ns from the fco of one two-c-ce ll cluster to the fci of the two- c-cell cluster immediately below it (see the "carry-chain logic" section on page 2-56 for more information). fastconnect for high-speed routing of logic sig nals, fastconnects can be used to build a short distance connection using a single antifuse ( figure 2-36 on page 2-62 ). fastconnects provide a maximum delay of 0.3 ns. the outputs of each logic module connect directly to the output tracks within a supercluster. signals on the output tracks can then be routed through a singl e antifuse connection to drive the inputs of logic modules either within one supe rcluster or in the supercl uster immediately below it. figure 2-35 ? directconnect and carryconnect
detailed specifications 2-62 revision 18 vertical and hori zontal routing vertical and horizontal tracks provide both local and long distance routing ( figure 2-37 on page 2-62 ). these tracks are composed of both short-distance, segmented routin g and across-chip routing tracks (segmented at core tile boundaries). the short- distance, segmented routing resources can be concatenated through antifuse connections to build longer routing tracks. these short-distance routing tracks can be used wit hin and between superclusters or between modules of non-adjacent superclusters. they can be connected to the out put tracks and to any logic module input (r-cell, c-cell, buffer, and tx module). the across-chip horizontal and vertical routing pr ovides long-distance routing resources. these resources interface with the rest of the routin g structures through the rx and tx modules ( figure 2-37 ). the rx module is used to drive signals from the ac ross-chip horizontal and vertical routing to the output tracks within the supercl uster. the tx module is used to dr ive vertical and horizontal across-chip routing from either short-distance horizontal tracks or from output tracks. the tx m odule can also be used to drive signals from vertical across-chip tracks to horizontal across-chip tracks and vice versa. figure 2-36 ? fastconnect routing figure 2-37 ? horizontal and vertical tracks
axcelerator family fpgas revision 18 2-63 timing characteristics table 2-65 ? ax125 predicted routing delays worst-case commercial cond itions vcca = 1.425 v, t j = 70c ?2 speed ?1 speed std speed units parameter description typical typical typical predicted routing delays t dc directconnect routing delay, fo1 0.11 0.12 0.15 ns t fc fastconnect routing delay, fo1 0.35 0.39 0.46 ns t rd1 routing delay for fo1 0.35 0.40 0.47 ns t rd2 routing delay for fo2 0.38 0.43 0.51 ns t rd3 routing delay for fo3 0.43 0.48 0.57 ns t rd4 routing delay for fo4 0.48 0.55 0.64 ns t rd5 routing delay for fo5 0.55 0.62 0.73 ns t rd6 routing delay for fo6 0.64 0.72 0.85 ns t rd7 routing delay for fo7 0.79 0.89 1.05 ns t rd8 routing delay for fo8 0.88 0.99 1.17 ns t rd16 routing delay for fo16 1.49 1.69 1.99 ns t rd32 routing delay for fo32 2.32 2.63 3.10 ns table 2-66 ? ax250 predicted routing delays worst-case commercial cond itions vcca = 1.425 v, t j = 70c ?2 speed ?1 speed std speed units parameter description typical typical typical predicted routing delays t dc directconnect routing delay, fo1 0.11 0.12 0.15 ns t fc fastconnect routing delay, fo1 0.35 0.39 0.46 ns t rd1 routing delay for fo1 0.39 0.45 0.53 ns t rd2 routing delay for fo2 0.41 0.46 0.54 ns t rd3 routing delay for fo3 0.48 0.55 0.64 ns t rd4 routing delay for fo4 0.56 0.63 0.75 ns t rd5 routing delay for fo5 0.60 0.68 0.80 ns t rd6 routing delay for fo6 0.84 0.96 1.13 ns t rd7 routing delay for fo7 0.90 1.02 1.20 ns t rd8 routing delay for fo8 1.00 1.13 1.33 ns t rd16 routing delay for fo16 2.17 2.46 2.89 ns t rd32 routing delay for fo32 3.55 4.03 4.74 ns
detailed specifications 2-64 revision 18 table 2-67 ? AX500 predicted routing delays worst-case commercial cond itions vcca = 1.425 v, t j = 70c ?2 speed ?1 speed std speed parameter description typical typical typical units predicted routing delays t dc directconnect routing delay, fo1 0.11 0.12 0.15 ns t fc fastconnect routing delay, fo1 0.35 0.39 0.46 ns t rd1 routing delay for fo1 0.39 0.45 0.53 ns t rd2 routing delay for fo2 0.41 0.46 0.54 ns t rd3 routing delay for fo3 0.48 0.55 0.64 ns t rd4 routing delay for fo4 0.56 0.63 0.75 ns t rd5 routing delay for fo5 0.60 0.68 0.80 ns t rd6 routing delay for fo6 0.84 0.96 1.13 ns t rd7 routing delay for fo7 0.90 1.02 1.20 ns t rd8 routing delay for fo8 1.00 1.13 1.33 ns t rd16 routing delay for fo16 2.17 2.46 2.89 ns t rd32 routing delay for fo32 3.55 4.03 4.74 ns table 2-68 ? ax1000 predicted routing delays worst-case commercial cond itions vcca = 1.425 v, t j = 70c ?2 speed ?1 speed std speed parameter description typical typical typical units predicted routing delays t dc directconnect routing delay, fo1 0.12 0.13 0.15 ns t fc fastconnect routing delay, fo1 0.35 0.39 0.46 ns t rd1 routing delay for fo1 0.45 0.51 0.60 ns t rd2 routing delay for fo2 0.53 0.60 0.71 ns t rd3 routing delay for fo3 0.56 0.63 0.74 ns t rd4 routing delay for fo4 0.63 0.71 0.84 ns t rd5 routing delay for fo5 0.73 0.82 0.97 ns t rd6 routing delay for fo6 0.99 1.13 1.32 ns t rd7 routing delay for fo7 1.02 1.15 1.36 ns t rd8 routing delay for fo8 1.48 1.68 1.97 ns t rd16 routing delay for fo16 2.57 2.91 3.42 ns t rd32 routing delay for fo32 4.24 4.81 5.65 ns
axcelerator family fpgas revision 18 2-65 table 2-69 ? ax2000 predicted routing delays worst-case commercial cond itions vcca = 1.425 v, t j = 70c ?2 speed ?1 speed std speed parameter description typical typical typical units predicted routing delays t dc directconnect routing delay, fo1 0.12 0.13 0.15 ns t fc fastconnect routing delay, fo1 0.35 0.39 0.46 ns t rd1 routing delay for fo1 0.50 0.56 0.66 ns t rd2 routing delay for fo2 0.59 0.67 0.79 ns t rd3 routing delay for fo3 0.70 0.80 0.94 ns t rd4 routing delay for fo4 0.76 0.87 1.02 ns t rd5 routing delay for fo5 0.98 1.11 1.31 ns t rd6 routing delay for fo6 1.48 1.68 1.97 ns t rd7 routing delay for fo7 1.65 1.87 2.20 ns t rd8 routing delay for fo8 1.73 1.96 2.31 ns t rd16 routing delay for fo16 2.58 2.92 3.44 ns t rd32 routing delay for fo32 4.24 4.81 5.65 ns
detailed specifications 2-66 revision 18 global resources one of the most important aspects of any fpga architecture is its global resources or clocks. the axcelerator family provides the user with flexible and easy-to-use global resources, without the limitations normally found in other fpga architectures. the ax architecture contains two types of global reso urces, the hclk (hardwired clock) and clk (routed clock). every axcelerator device is provided with f our hclks and four clks for a total of eight clocks, regardless of device density. hardwired clocks the hardwired (hclk) is a low-skew network that c an directly drive the clock inputs of all sequential modules (r-cells, i/o registers, a nd embedded ram/fifos) in the device with no antifuse in the path. all four hclks are available everywhere on the chip. timing characteristics table 2-70 ? ax125 dedicated (hardwired) array clock networks worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed units parameter description mi n. max. min. max. min. max. dedicated (hardwired) array clock networks t hckl input low to high 3.02 3.44 4.05 ns t hckh input high to low 3.03 3.46 4.06 ns t hpwh minimum pulse width high 0.58 0.65 0.77 ns t hpwl minimum pulse width low 0.52 0.59 0.69 ns t hcksw maximum skew 0.06 0.07 0.08 ns t hp minimum period 1.15 1.31 1.54 ns t hmax maximum frequency 870 763 649 mhz table 2-71 ? ax250 dedicated (hardwired) array clock networks worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed units parameter description min.max.min.max.min.max. dedicated (hardwired) array clock networks t hckl input low to high 2.57 2.93 3.45 ns t hckh input high to low 2.61 2.97 3.50 ns t hpwh minimum pulse width high 0.58 0.65 0.77 ns t hpwl minimum pulse width low 0.52 0.59 0.69 ns t hcksw maximum skew 0.06 0.07 0.08 ns t hp minimum period 1.15 1.31 1.54 ns t hmax maximum frequency 870 763 649 mhz
axcelerator family fpgas revision 18 2-67 table 2-72 ? AX500 dedicated (hardwired) array clock networks worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed parameter description min. max. min. max. min. max. units dedicated (hardwired) array clock networks t hckl input low to high 2.35 2.68 3.15 ns t hckh input high to low 2.44 2.79 3.27 ns t hpwh minimum pulse width high 0.58 0.65 0.77 ns t hpwl minimum pulse width low 0.52 0.59 0.69 ns t hcksw maximum skew 0.06 0.07 0.08 ns t hp minimum period 1.15 1.31 1.54 ns t hmax maximum frequency 870 763 649 mhz table 2-73 ? ax1000 dedicated (hardwired) array clock networks worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed parameter description min. max. min. max. min. max. units dedicated (hardwired) array clock networks t hckl input low to high 3.02 3.44 4.05 ns t hckh input high to low 3.03 3.46 4.06 ns t hpwh minimum pulse width high 0.58 0.65 0.77 ns t hpwl minimum pulse width low 0.52 0.59 0.69 ns t hcksw maximum skew 0.06 0.07 0.08 ns t hp minimum period 1.15 1.31 1.54 ns t hmax maximum frequency 870 763 649 mhz table 2-74 ? ax2000 dedicated (hardwired) array clock networks worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed parameter description min.max.min.max.min.max.units dedicated (hardwired) array clock networks t hckl input low to high 3.02 3.44 4.05 ns t hckh input high to low 3.03 3.46 4.06 ns t hpwh minimum pulse width high 0.58 0.65 0.77 ns t hpwl minimum pulse width low 0.52 0.59 0.69 ns t hcksw maximum skew 0.06 0.07 0.08 ns t hp minimum period 1.15 1.31 1.54 ns t hmax maximum frequency 870 763 649 mhz
detailed specifications 2-68 revision 18 routed clocks the routed clock (clk) is a low-skew network that c an drive the clock inputs of all sequential modules in the device (logically equivalent to the hclk), but ha s the added flexibility in that it can drive the s0 (enable), s1, pset, and clr input of a register (r-cells and i/o registers) as well as any of the inputs of any c-cell in the device. th is allows clks to be used not only as clocks, but also for other global signals or high fanout nets. all four clks are available everywhere on the chip. timing characteristics table 2-75 ? ax125 routed array clock networks worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed units parameter description mi n. max. min. max. min. max. routed array clock networks t rckl input low to high 3.08 3.50 4.12 ns t rckh input high to low 3.13 3.56 4.19 ns t rpwh minimum pulse width high 0.57 0.64 0.75 ns t rpwl minimum pulse width low 0.52 0.59 0.69 ns t rcksw maximum skew 0.35 0.39 0.46 ns t rp minimum period 1.15 1.31 1.54 ns t rmax maximum frequency 870 763 649 mhz table 2-76 ? ax250 routed array clock networks worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed units parameter description min. max. min. max. min. max. routed array clock networks t rckl input low to high 2.52 2.87 3.37 ns t rckh input high to low 2.59 2.95 3.47 ns t rpwh minimum pulse width high 0.57 0.64 0.75 ns t rpwl minimum pulse width low 0.52 0.59 0.69 ns t rcksw maximum skew 0.35 0.39 0.46 ns t rp minimum period 1.15 1.31 1.54 ns t rmax maximum frequency 870 763 649 mhz
axcelerator family fpgas revision 18 2-69 table 2-77 ? AX500 routed array clock networks worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed parameter description min. m ax. min. max. min. max. units routed array clock networks t rckl input low to high 2.31 2.63 3.09 ns t rckh input high to low 2.44 2.78 3.27 ns t rpwh minimum pulse width high 0.57 0.64 0.75 ns t rpwl minimum pulse width low 0.52 0.59 0.69 ns t rcksw maximum skew 0.35 0.39 0.46 ns t rp minimum period 1.15 1.31 1.54 ns t rmax maximum frequency 870 763 649 mhz table 2-78 ? ax1000 routed array clock networks worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed parameter description min. max. min. max. min. max. units routed array clock networks t rckl input low to high 3.08 3.50 4.12 ns t rckh input high to low 3.13 3.56 4.19 ns t rpwh minimum pulse width high 0.57 0.64 0.75 ns t rpwl minimum pulse width low 0.52 0.59 0.69 ns t rcksw maximum skew 0.35 0.39 0.46 ns t rp minimum period 1.15 1.31 1.54 ns t rmax maximum frequency 870 763 649 mhz table 2-79 ? ax2000 routed array clock networks worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed parameter description min. max. min. max. min. max. units routed array clock networks t rckl input low to high 3.08 3.50 4.12 ns t rckh input high to low 3.13 3.56 4.19 ns t rpwh minimum pulse width high 0.57 0.64 0.75 ns t rpwl minimum pulse width low 0.52 0.59 0.69 ns t rcksw maximum skew 0.35 0.39 0.46 ns t rp minimum period 1.15 1.31 1.54 ns t rmax maximum frequency 870 763 649 mhz
detailed specifications 2-70 revision 18 global resource distribution at the root of each global resource is a pll. there are two groups of four plls for every device. one group, located at the center of t he north edge (in the i/o ring) of the chip, sources the four hclks. the second group, located at the cent er of the south edge (again in t he i/o ring), sources the four clks ( figure 2-38 ). regardless of the type of global resource, hclk or clk, each of the eight resources reach the clocktiledist (ctd) cluster located at the center of every core tile with zero skew. from the clocktiledist cluster, all four hclks and four clks are distributed through the core tile ( figure 2-39 ). figure 2-38 ? pll group figure 2-39 ? example of hclk and clk di stributions on the ax2000 pll cluster pll cluster pn pn pn pn pn pn pn pn hclka hclkb hclkc hclkd clke pll clkf clkg clkh pll pll pll pll pll pll pll pll group hclk clk pll group 4 4 clocktiledist cluster
axcelerator family fpgas revision 18 2-71 the clocktiledist cluster contains an hclkmux (hm) module for each of the four hclk trees and a clkmux (cm) module for each of the clk trees. the hclk bran ches then propagate horizontally through the middle of the core tile to hclkcoldist (hd) modules in every supercluster column. the clk branches propagate vertically throu gh the center of the core tile to clkrowdist (rd) modules in every supercluster row. together, the hclk and clk branch es provide for a low-skew global fanout within the core tile ( figure 2-40 and figure 2-41 ). figure 2-40 ? ctd, cd, and hd module layout figure 2-41 ? hclk and clk distribution within a core tile
detailed specifications 2-72 revision 18 the hm and cm modules can select between: ? the hclk or clk source respectively ? a local signal routed on generic routing resources this allows each core tile to have eight clocks independent of the other core tiles in the device. both hclk and clk are segmentable, meaning that individual branches of the global resource can be used independently. like the hm and cm modules, the hd and rd modules can select between: ? the hclk or clk source from the hm or cm module respectively ? a local signal routed on generic routing resources the ax architecture is capable of supporting a large number of local clocks?24 segments per hclk driving north-south and 28 segments per clk driving east-west per core tile. microsemi's designer software?s place-and-route ta kes advantage of the segmented clock structure found in axcelerator devices by turning off any unus ed clock segments. this results in not only better performance but also lower power consumption. global resource access macros global resources can be driven by one of three sources: external pad(s), an internal net, or the output of a pll. these connections can be made by using on e of three types of macros: clkbuf, clkint, and pllclk. clkbuf and hclkbuf clkbuf (hclkbuf) is used to drive a clk (hclk) from external pads. these macros can be used either generically or with the specific i/o st andard desired (e.g. clkbuf_lvcmos25, hclkbuf_lvds, etc.) ( figure 2-42 ). package pins clkep and clken are associated with clke; package pins hclkap and hclkan are associated with hclka, etc. note that when clkbuf (hclkbuf) is used with a si ngle-ended i/o standard, it must be tied to the p-pad of the clk (hclk) package pin. in this case , the clk (hclk) n-pad can be used for user signals. clkint and hclkint clkint (hclkint) is used to access the clk (hcl k) resource internally from the user signals ( figure 2-43 ). figure 2-42 ? clkbuf and hclkbuf figure 2-43 ? clkint and hclkint p n clkbuf hclkbuf clock network clkint hclkint clock network logic
axcelerator family fpgas revision 18 2-73 pllrclk and pllhclk pllrclk (pllhclk) is used to drive global resource clk (hclk) from a pll ( figure 2-44 ). using global resources with plls each global resource has an associated pll at its ro ot. for example, plla can drive hclka, plle can drive clke, etc. ( figure 2-45 ). in addition, each clock pin of the package can be used to drive either its associated global resource or pll. for example, package pins clkep and clken can drive either the refclk input of plle or clke. there are two macros required when interfacing th e embedded plls with the global resources: pllint and pllout. pllint this macro is used to drive the refclk in put of the pll internally from user signals. pllout this macro is used to connect either the clk1 or clk2 output of a pll to the regular routing network ( figure 2-46 ). figure 2-44 ? pllrclk and pllhclk figure 2-45 ? example of hclka driven from a pll with external clock source figure 2-46 ? example of pllint and pllout usage pllrclk pllhclk clock network clk1 clk2 fb refclk pll hclkap hclkan pllhclk hclka network clk1 clk2 fb refclk plla pllint pllhclk pllout hclka network clk1 clk2 fb refclk plla logic logic
detailed specifications 2-74 revision 18 implementation example: figure 2-47 shows a complex clock distribution example. the reference clock (refclk) of plle is being sourced from non-clock signal pins (inbuf to pllint ). the clk1 output of plle is being fed to the refclk input of pllf. the clk2 output of plle is driv ing logic (via pllout). in turn, this logic is driving the global resource clke. pllf is driving both clkf and clkg global resources. figure 2-47 ? complex clock distribution example clk1 clk2 fb refclk pllf clk1 clk2 fb refclk plle pllint inbuf non-clock pins p n pllrclk pllout pllrclk pllrclk clke logic clkf clkg clkint
axcelerator family fpgas revision 18 2-75 axcelerator clock management system introduction each member of the axcelerator family 6 contains eight phase-locked l oop (pll) blocks which perform the following functions: ? programmable delay (32 steps of 250 ps) ? clock skew minimization ? clock frequency synthesis each pll has the following key features: ? input frequency range ? 14 to 200 mhz ? output frequency range ? 20 mhz to 1 ghz ? output duty cycle range ? 45% to 55% ? maximum long-term jitter ? 1% or 100ps (whichever is greater) ? maximum short-term jitter ? 50ps + 1% of output frequency ? maximum acquisition time (lock) ? 20s physical implementation the eight pll blocks are arranged in two groups of fo ur. one group is located in the center of the northern edge of the chip, while the second group is centered on the southern edge. the northern group is associated with the four hclk networks (e.g. pl la can drive hclka), while the southern group is associated with the four clk networks (e.g. plle can drive clke). each pll cell is connected to two i/o pads and a pll cluster that interfaces with the fpga core. figure 2-48 illustrates a pll block. the vccpll pin should be connected to a 1.5v power supply through a 250 resistor. furthermore, 0.1 f and 10 f decoupling capacitors should be connected across the vccpll and vcomppll pins. note: the vcomppll pin should never be grounded ( figure 2-2 on page 2-9 )! the i/o pads associated wit h the pll can also be configured for regul ar i/o functions except when it is used as a clock buffer. the i/o pads can be configured in all the modes available to the regular i/o pads in the same i/o bank. in particular, the [h]clkxp pad can be configured as a differential pair, 6. ax2000-cq256 does not support operation of the phase-locked loops. this is in order to support full pin compatibility with rtax2000s/sl-cq256. figure 2-48 ? pll block diagram refclk fb lock 6 divj clk1 clk2 fbmuxsel delayline divj lowfreq osc 56 3 delay line powerdown delay line pll /i delay match /j delay match /i /j
detailed specifications 2-76 revision 18 single-ended, or voltage-referenced standard. the [h ]clkxn pad can only be used as a differential pair with [h]clkxp. the block marked ?/i delay match? is a fixed delay equal to that of the i divider. the ?/j delay match? block has the same function as its j divider counterpart. functional description figure 2-48 on page 2-75 illustrates a block diagram of the pll. the pll contains two dividers, i and j, that allow frequency scaling of the clock signal: ? the i divider in the feedback path allows multiplic ation of the input clock by integer factors ranging from 1 to 64, and the resultant frequency is available at the output of the pll block. ? the j divider divides the pll output by integer fa ctors ranging from 1 to 64, and the divided clock is available at clk1. ? the two dividers together can implement any co mbination of multiplication and division up to a maximum frequency of 1 ghz on clk1. both the clk1 and clk2 outputs have a fixed 50/50 duty cycle. ? the output frequencies of the two clocks are given by the following formulas (f ref is the reference clock frequency): f clk1 = f ref * (divideri) / (dividerj) eq 4 f clk2 = f ref * (divideri) eq 5 ? clk2 provides the pll output directly?without division the input and output frequency ranges are selected by lowfreq and osc(2:0), respectively. these functions and their possible values are detailed in table 2-80 on page 2-77 . the delay lines shown in figure 2-48 on page 2-75 are programmable. the feedback clock path can be delayed (using the five delayline bits) relative to the reference clock (or vice versa) by up to 3.75 ns in increments of 250 ps. table 2-80 on page 2-77 describes the usage of thes e bits. the delay increments are independent of frequency, so this results in phase changes that vary with frequency. the delay value is highly dependent on v cc and the speed grade. figure 2-49 is a logical diagram of the various control signals to the pll and shows how the pll interfaces with the global and r outing networks of the fpga. note that not all signals are user- accessible. these non-user-accessible signals are us ed by the place-and-route tool to control the configuration of the pll. the user gains access to these control signals either based upon the connections built in the user's desi gn or through the special macros ( table 2-84 on page 2-81 ) inserted into the design. for example, connecting the macr o pllout to clk2 will control the outsel signal. note: not all signals are available to the user. figure 2-49 ? pll logical interface refclk fb clk1 clk2 refsel rootsel fbmuxsel [h]clkint [h]clkxp [h]clkxn i/o core net clk net fbint 0 0 1 1 2 3 clkint clk1 (plln-1) clk1 (plln-1) [h]clk to plln+1 pllsel outsel clk out (routed net out pin) pll
axcelerator family fpgas revision 18 2-77 table 2-80 ? pll interface signals signal name type user accessible allowable values function refclk input yes reference clock for the pll fb input yes feedback port for the pll powerdown input yes pll power down control 0 pll powered down 1 pll active divi[5:0] input yes 1 to 64, in unsigned binary notation offset by -1 sets value for feedback divider (multiplier) divj[5:0] input yes sets value for clk1 divider lowfreq input yes input fr equency range selector 0 50?200 mhz 1 14?50 mhz osc[2:0] input yes output frequency range selector xx0 400?1000 mhz 001 200?400 mhz 011 100?200 mhz 101 50?100 mhz 111 20?50 mhz delayline[4:0] input yes ?15 to +15 (increments), in signed-and- magnitude binary representation clock delay (positive/negative) in increments of 250 ps, with maximum value of 3.75 ns fbmuxsel input no selects the source for the feedback input refsel input no selects the source for the reference clock outsel input no selects the source for the routed net output pllsel input no rootsel & pllsel are used to select the source of the global clock network rootsel input no lock output yes high value indicates pll has locked clk1 output yes pll clock output clk2 output yes pll clock output note: if the input refclk is taken outside its operati ng range, the outputs lock, clk1 and clk2 are indeterminate.
detailed specifications 2-78 revision 18 pll configurations the following rules apply to the different pll inputs and outputs: reference clock the refclk can be driven by ( figure 2-50 ): 1. global routed clocks (clke/f/g/h) or user-created clock network 2. clk1 output of an adjacent pll 3. [h]clkxp (single-ended or voltage-referenced) 4. [h]clkxp/[h]clkxn pair (differe ntial modes like lvpecl or lvds) feedback clock the feedback clock can be driven by ( figure 2-51 on page 2-78 ): 1. global routed clocks (clke/f/g/h) or user-created clock network 2. external [h]clkxp/n i/o pad(s) from the adjacent pll cell 3. an internal signal from the pll block figure 2-50 ? reference clock connections figure 2-51 ? feedback clock connections non-clock pins p n inbuf pll refclk refclk pll refclk pll pll clk1 regular, lvpecl, or lvds iopad any macro from the core, except hclk nets for cascading logic pll fb fb pll pllout/pllrclk any macro except hclk macros
axcelerator family fpgas revision 18 2-79 clk1 and clk2 both pll outputs, clk1 and clk2, can be used to drive a global resource, an adjacent pll refclk input, or a net in the fpga core. no t all drive combinations are possible ( ta b l e 2 - 8 1 ). restrictions on clk1 and clk2 ? when both are driving global resources, they must be driving the same type of global resource (i.e. either hclk or clk). ? only one can drive a routed net at any given time. table 2-82 and table 2-83 specify all the possible clk1 and cl k2 connections for the north and south plls. hclk1 and hclk2 are used to denote the diff erent hclk networks when two are being driven at the same time by a single pll (note that hclk1 is the primary clock resource associated with the pll, and hclk2 is the clock resource a ssociated with the adjacent pll). likewise, clk1 and clk2 are used to denote the different clk networks when two are be ing driven at the same time by a single pll ( figure 2-48 on page 2-75 ). table 2-81 ? pll general connections rules clk1 clk2 hclk hclk clk clk hclk routed net output routed net output hclk hclk none none hclk clk none none clk note: the pll outputs remain low when refclk is constant (either low or high). table 2-82 ? north pll connections clk1 clk2 hclk1 routed net hclk1 unused hclk2 hclk1 hclk2 routed net hclk2 both hclk1 and routed net hclk2 unused unused hclk1 unused routed net unused both hclk1 and routed net unused unused routed net hclk1 routed net unused both hclk1 and hclk2 routed net both hclk1 and hclk2 unused both hclk1 and routed net unusable both hclk2 and routed net hclk1 both hclk2 and routed net unused hclk1, hclk2, and routed net unusable note: designer software currently does not support all of these connec tions. only exclusive connections where one output connects to a single net are s upported at this time (e.g.clk1 driving hclk1, and hclk2 is not supported).
detailed specifications 2-80 revision 18 table 2-83 ? south pll connections clk1 clk2 clk1 routed net clk1 unused clk2 clk1 clk2 routed net clk2 both clk1 and routed net clk2 unused unused clk1 unused routed net unused both clk1 and routed net unused unused routed net clk1 routed net unused both clk1 and clk2 routed net both clk1 and clk2 unused both clk1 and routed net unusable both clk2 and routed net clk1 both clk2 and routed net unused clk1, clk2, and routed net unusable note: designer software currently does not support all of these connec tions. only exclusive connections where one output connects to a single net are su pported at this time (e.g., clk1 driving both clk1 and clk2 is not supported).
axcelerator family fpgas revision 18 2-81 special pll macros table 2-84 shows the macros used to connect the refclk input and clk1 and clk2 outputs using the different routing resources. table 2-84 ? pll special macros macro name usage pllint connects refclk to a regular routed net or a pad. pllrclk connects clk1 or clk2 to the clk network. pllhclk connects clk1 or clk2 to the hclk network. pllout connects clk1 or clk2 to a regular routed net. table 2-85 ? electrical specifications parameter value notes frequency ranges reference frequency (min.) 14 mhz lowest input frequency reference frequency (max.) 200 mhz highest input frequency osc frequency (min.) 20 mhz lowest output frequency osc frequency (max.) 1 ghz highest output frequency jitter long-term jitter (max.) 1% percentage of period, low reference clock frequencies long-term jitter (max.) 100ps high reference clock frequencies short-term jitter (max.) 50ps+1% percentage of output frequency acquisition time (lock) from cold start acquisition time (max.)* 400 cycles period of low reference clock frequencies acquisition time (max.)* 1.5 s high reference clock frequencies power consumption analog supply current (low freq.) 200 a current at minimum oscillator frequency analog supply current (high freq.) 200 a frequency-dependent current digital supply current (low freq.) 0.5 a/mhz current at maximum oscillator frequency, unloaded digital supply current (high freq.) 1 a/mhz frequency-dependent current duty cycle minimum output duty cycle 45% maximum output duty cycle 55% note: *the lock bit remains low until refclk reaches the minimum input frequency.
detailed specifications 2-82 revision 18 user flow there are two methods of including a pll in a design: ? the recommended method of using a pll is to create custom pll blocks using microsemi's macro generator, smartgen, that can be instantiated in a design. ? the alternative method is to instantiate one of the generic library primitives (pll or pllfb) into either a schematic or hdl netlist, using inverter s for polarity control and tying all unused address and data bits to ground. timing model note: t pclk is the delay in the clock signal figure 2-52 ? pll model clk clk1 lock clk2 configuration pins divideri/dividerj delay line fbmux osc 63 5 6 fb t pclk *
axcelerator family fpgas revision 18 2-83 sample implementations frequency synthesis figure 2-53 illustrates an example where the pll is used to multiply a 155.5 mhz external clock up to 622 mhz. note that the same pll schematic coul d use an external 350 mhz clock, which is divided down to 155 mhz by the fpga internal logic. figure 2-54 illustrates the pll using both dividers to synt hesize a 133 mhz output clock from a 155 mhz input reference clock. the input frequency of 155 mhz is multiplied by 6 and divided by 7, giving a clk1 output frequency of 132.86 mhz. when dividers are us ed, a given ratio can be generated in multiple ways, allowing the user to stay within the operating frequency ranges of the pll. adjustable clock delay figure 2-55 illustrates using the pll to delay the refer ence clock by employing one of the adjustable delay lines. in this case, the output clock is delayed relative to the reference clock. delaying the reference clock relative to the output clock is accomplished by using the delay line in the feedback path. figure 2-53 ? using the pll 155.5 mhz in, 622 mhz out delay line pll delay line refclk fb /i 6 /j 6 clk1 power-down lock clk2 fbmuxsel 5 divideri delayline dividerj lowfreq 3 osc + 4 155.5 mhz 622 mhz /i delay match /j delay match
detailed specifications 2-84 revision 18 figure 2-54 ? using the pll 155 mhz in, 133 mhz out figure 2-55 ? using the pll delaying the reference clock 5 delay line pll delay line refclk fb /i 6 /j 6 clk1 power-down lock clk2 fbmuxsel divideri delayline dividerj lowfreq 3 osc + 6 155 mhz 132.8 mhz 155 mhz 155 mhz 930 mhz /7 yes /i delay match /j delay match delay line delay line pll refclk fb 6 /j 6 clk1 powerdown lock clk2 fbmuxsel 5 divideri delayline dividerj lowfreq 3 osc 1 133 mhz 133 mhz /j /i delay match /j delay match
axcelerator family fpgas revision 18 2-85 clock skew minimization figure 2-56 indicates how feedback from the clock network can be used to create minimal skew between the distributed clock network and the input clock. the i nput clock is fed to the reference clock input of the pll. the output clock (clk2) feeds a routed clock ne twork. the feedback input to the pll uses a clock input delayed by a routing network. the pll then adjusts the phase of the input clock to match the delayed clock, thus prov iding nearly zero effective skew betw een the two clocks. refer to the axcelerator family pll and clock management application note for more information. figure 2-56 ? using the pll for clock deskewing q clr delay line pll refclk fb 6 /j 6 clk1 power-down input clock clock network lock clk2 fbmuxsel 5 divideri delayline dividerj lowfreq 3 osc 1 133 mhz 133 mhz d q set 133 mhz delay line /i /i delay match /i delay match
detailed specifications 2-86 revision 18 embedded memory the ax architecture provides extensive, high-speed memory resources to the user. each 4,608 bit block of ram contains its own embedded fifo controller, a llowing the user to configure each block as either ram or fifo. to meet the needs of hi gh performance designs, the memory bl ocks operate in syn chronous mode for both read and write operations. however, the read and write clocks are completely independent, and each may operate up to and above 500 mhz. no additional core logic resources are required to cascade the address and data buses when cascading different ram blocks. dedicated ro uting runs along each column of ram to facilitate cascading. the ax memory block includes dedicated fifo contro l logic to generate internal addresses and external flag logic (full, empty, afull, aempty). since read and write operations can occur asynchronously to one another, special control circuitry is included to prevent metastability, overflow, and underflow. a block diagram of the memory module is illustrated in figure 2-57 . during ram operation, read (ra) and write (wa) addresses are sourced by user logic and the fifo controller is ignored. in fifo mode, the internal addresses are gen erated by the fifo controller and routed to the ram array by internal muxes. enable s with programmable polarity are provided to create upper address bits for cascading up to 16 memory blocks. when cascading memory blocks, the bussed signals wa, wd, wen, ra, rd, and ren are internally linked to eliminate external routing congestion. figure 2-57 ? axcelerator memory module ra [k:0] rd [(n-1):0] ren rclk wd [(m-1):0] wa [j:0] wen wclk pipe rw [2:0] ww [2:0]
axcelerator family fpgas revision 18 2-87 ram each memory block consists of 4,608 bits that can be organized as 128x36, 256x18, 512x9, 1kx4, 2kx2, or 4kx1 and are cascadable to create larger memo ry sizes. this allows built-in bus width conversion ( table 2-86 ). each block has independent read and write ports which enable simultaneous read and write operations. clocks the rclk and the wclk have independent source polarit y selection and can be sourced by any global or local signal. ram configurations the ax architecture allows the read side and writ e side of rams to be organized independently, allowing for bus conversion. for example, the write side can be set to 256x18 and the read side to 512x9. both the write width and read width for the ram blocks can be specified independently and changed dynamically with the ww (write width) and rw (read wi dth) pins. the d x w different configurations are: 128 x 36, 256 x 18, 512 x 9, 1k x 4, 2k x 2, and 4k x 1. the allowable rw and ww values are shown in table 2-87 . when widths of one, two, and four are selected, the ninth bit is unused. for example, when writing nine- bit values and reading four-bit values, only the first four bits and the second four bits of each nine-bit value are addressable for read operations. the ninth bit is not accessible. conver sely, when writing four- bit values and reading nine-bit values, the ni nth bit of a read operation will be undefined. table 2-86 ? memory block wxd options data-word (in bits) depth address bus data bus 1 4,096 ra/wa[11:0] rd/wd[0] 2 2,048 ra/wa[10:0] rd/wd[1:0] 4 1,024 ra/wa[9:0] rd/wd[3:0] 9 512 ra/wa[8:0] rd/wd[8:0] 18 256 ra/wa[7:0] rd/wd[17:0] 36 128 ra/wa[6:0] rd/wd[35:0] table 2-87 ? allowable rw and ww values rw(2:0) ww(2:0) d x w 000 000 4k x 1 001 001 2k x 2 010 010 1k x 4 011 011 512 x 9 100 100 256 x 18 101 101 128 x 36 11x 11x reserved
detailed specifications 2-88 revision 18 note that the ram blocks employ little-endian byte order for read and write operations. modes of operation there are two read mode s and one write mode: ? read nonpipelined (synchronous ? one clock edge) ? read pipelined (synchronous ? two clock edges) ? write (synchronous ? one clock edge) in the standard re ad mode, new data is driven onto the rd bus in the clo ck cycle immediately following ra and ren valid. the read address is registered on the read-port active-clock edge and data appears at read-data after the ram access time. setting the pipe to off enables this mode. the pipelined mode incurs an additional clock delay from address to data, but enables operation at a much higher frequency. the read-address is registered on the read-port active-clock edge, and the read data is registered and appears at rd after the second read clock edge. setting the pipe to on enables this mode. on the write active-clock edge, the write data are written into the sr am at the write address when wen is high. the setup time of the writ e address, write enables, and write data are minimal with respect to the write clock. write and read transfers are described with timing requirements beginning in the "timing characteristics" section on page 2-89 . table 2-88 ? ram signal description signal direction description wclk input write clock (can be active on either edge). wa[j:0] input write address bus.the value j is dependent on the ram configuration and the number of cascaded memory blocks. t he valid range for j is from 6 to15. wd[m-1:0] input write data bus. the value m is dependent on the ram configuration and can be 1, 2, 4, 9, 18, or 36. rclk input read clock (can be active on either edge). ra[k:0] input read address bus. the value k is dependent on the ram configuration and the number of cascaded memory blocks. the valid range for k is from 6 to 15. rd[n-1:0] output read data bus. the value n is dependent on the ram configuration and can be 1, 2, 4, 9, 18, or 36. ren input read enable. when this signal is valid on the active edge of the clock, data at location ra will be driven onto rd. wen input write enable. when this signal is valid on the active edge of the clock, wd data will be written at location wa. rw[2:0] input width of the read operation dataword. ww[2:0] input width of the write operation dataword. pipe input sets the pipe option to be on or off.
axcelerator family fpgas revision 18 2-89 timing characteristics figure 2-58 ? sram model figure 2-59 ? ram write timing waveforms figure 2-60 ? ram read timing waveforms wd rd ra ren wa wclk rclk wen wclk t wckp t wxxsu t wxxhd t wckh t wckl wa<11:0>, wd<35:0>, wen<4:0> rclk ra<11:0>, ren<4:0> rd <35:0> t rxxsu t rxxhd t rckp t rckh t rckl t rck2rd1 t rck2rd2
detailed specifications 2-90 revision 18 table 2-89 ? one ram block worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed units parameter description min. max. min. max. min. max. write mode t wdasu write data setup vs. wclk 1.08 1.23 1.45 ns t wdahd write data hold vs. wclk 0.22 0.25 0.30 ns t wadsu write address setup vs. wclk 1.08 1.23 1.45 ns t wadhd write address hold vs. wclk 0.00 0.00 0.00 ns t wensu write enable setup vs. wclk 1.08 1.23 1.45 ns t wenhd write enable hold vs. wclk 0.22 0.25 0.30 ns t wckh wclk minimum high pulse width 0.75 0.75 0.75 ns t wclk wclk minimum low pulse width 0.88 0.88 0.88 ns t wckp wclk minimum period 1.63 1.63 1.63 ns read mode t radsu read address setup vs. rclk 0.81 0.92 1.08 ns t radhd read address hold vs. rclk 0.00 0.00 0.00 ns t rensu read enable setup vs. rclk 0.81 0.92 1.08 ns t renhd read enable hold vs. rclk 0.00 0.00 0.00 ns t rck2rd1 rclk-to-out (pipelined) 1.32 1.51 1.77 ns t rck2rd2 rclk-to-out (non-pipelined) 2.16 2.46 2.90 ns t rclkh rclk minimum high pulse width 0.77 0.77 0.77 ns t rclkl rclk minimum low pulse width 0.93 0.93 0.93 ns t rckp rclk minimum period 1.70 1.70 1.70 ns note: timing data for this single block ram has a depth of 4, 096. for all other combinations, use microsemi?s timing software.
axcelerator family fpgas revision 18 2-91 table 2-90 ? two ram blocks cascaded worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed parameter description min. m ax. min. max. min. max. units write mode t wdasu write data setup vs. wclk 1.39 1.59 1.87 ns t wdahd write data hold vs. wclk 0.00 0.00 0.00 ns t wadsu write address setup vs. wclk 1.39 1.59 1.87 ns t wadhd write address hold vs. wclk 0.00 0.00 0.00 ns t wensu write enable setup vs. wclk 1.39 1.59 1.87 ns t wenhd write enable hold vs. wclk 0.00 0.00 0.00 ns t wckh wclk minimum high pulse width 0.75 0.75 0.75 ns t wclk wclk minimum low pulse width 1.76 1.76 1.76 ns t wckp wclk minimum period 2.51 2.51 2.51 ns read mode t radsu read address setup vs. rclk 1.71 1.94 2.28 ns t radhd read address hold vs. rclk 0.00 0.00 0.00 ns t rensu read enable setup vs. rclk 1.71 1.94 2.28 ns t renhd read enable hold vs. rclk 0.00 0.00 0.00 ns t rck2rd1 rclk-to-out (pipelined) 1.43 1.63 1.92 ns t rck2rd2 rclk-to-out (non-pipelined) 2.26 2.58 3.03 ns t rclkh rclk minimum high pulse width 0.73 0.73 0.73 ns t rclkl rclk minimum low pulse width 1.89 1.89 1.89 ns t rckp rclk minimum period 2.62 2.62 2.62 ns note: timing data for these two cascaded ram blocks uses a depth of 8,192. for all other combinations, use microsemi?s timing software.
detailed specifications 2-92 revision 18 table 2-91 ? four ram blocks cascaded worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed parameter description min. max. min. max. min. max. units write mode t wdasu write data setup vs. wclk 2.37 2.70 3.17 ns t wdahd write data hold vs. wclk 0.00 0.00 0.00 ns t wadsu write address setup vs. wclk 2.37 2.70 3.17 ns t wadhd write address hold vs. wclk 0.00 0.00 0.00 ns t wensu write enable setup vs. wclk 2.37 2.70 3.17 ns t wenhd write enable hold vs. wclk 0.00 0.00 0.00 ns t wckh wclk minimum high pulse width 0.75 0.75 0.75 ns t wclk wclk minimum low pulse width 2.51 2.51 2.51 ns t wckp wclk minimum period 3.26 3.26 3.26 ns read mode t radsu read address setup vs. rclk 3.08 3.51 4.13 ns t radhd read address hold vs. rclk 0.00 0.00 0.00 ns t rensu read enable setup vs. rclk 3.08 3.51 4.13 ns t renhd read enable hold vs. rclk 0.00 0.00 0.00 ns t rck2rd1 rclk-to-out (pipelined) 2.36 2.69 3.16 ns t rck2rd2 rclk-to-out (non-pipelined) 2.83 3.23 3.79 ns t rclkh rclk minimum high pulse width 0.73 0.73 0.73 ns t rclkl rclk minimum low pulse width 2.96 2.96 2.96 ns t rckp rclk minimum period 3.69 3.69 3.69 ns note: timing data for these four cascaded ram blocks uses a depth of 16,384. for all other combinations, use microsemi?s timing software.
axcelerator family fpgas revision 18 2-93 table 2-92 ? eight ram blocks cascaded worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed parameter description min. m ax. min. max. min. max. units write mode t wdasu write data setup vs. wclk 5.78 6.58 7.74 ns t wdahd write data hold vs. wclk 0.00 0.00 0.00 ns t wadsu write address setup vs. wclk 5.78 6.58 7.74 ns t wadhd write address hold vs. wclk 0.00 0.00 0.00 ns t wensu write enable setup vs. wclk 5.78 6.58 7.74 ns t wenhd write enable hold vs. wclk 0.00 0.00 0.00 ns t wckh wclk minimum high pulse width 0.75 0.75 0.75 ns t wclk wclk minimum low pulse width 5.13 5.13 5.13 ns t wckp wclk minimum period 5.88 5.88 5.88 ns read mode t radsu read address setup vs. rclk 6.75 7.69 9.04 ns t radhd read address hold vs. rclk 0.00 0.00 0.00 ns t rensu read enable setup vs. rclk 6.75 7.69 9.04 ns t renhd read enable hold vs. rclk 0.00 0.00 0.00 ns t rck2rd1 rclk-to-out (pipelined) 3.39 3.86 4.54 ns t rck2rd2 rclk-to-out (non-pipelined) 4.93 5.62 6.61 ns t rclkh rclk minimum high pulse width 0.73 0.73 0.73 ns t rclkl rclk minimum low pulse width 5.77 5.77 5.77 ns t rckp rclk minimum period 6.50 6.50 6.50 ns note: timing data for these eight cascaded ram blocks uses a depth of 32,768. for all other combinations, use microsemi?s timing software.
detailed specifications 2-94 revision 18 table 2-93 ? sixteen ram blocks cascaded worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed parameter description min. max. min. max. min. max. units write mode t wdasu write data setup vs. wclk 16.54 18.84 22.15 ns t wdahd write data hold vs. wclk 0.00 0.00 0.00 ns t wadsu write address setup vs. wclk 16.54 18.84 22.15 ns t wadhd write address hold vs. wclk 0.00 0.00 0.00 ns t wensu write enable setup vs. wclk 16.54 18.84 22.15 ns t wenhd write enable hold vs. wclk 0.00 0.00 0.00 ns t wckh wclk minimum high pulse width 0.75 0.75 0.75 ns t wclk wclk minimum low pulse width 13.40 13.40 13.40 ns t wckp wclk minimum period 14.15 14.15 14.15 ns read mode t radsu read address setup vs. rclk 18.13 20.65 24.27 ns t radhd read address hold vs. rclk 0.00 0.00 0.00 ns t rensu read enable setup vs. rclk 18.13 20.65 24.27 ns t renhd read enable hold vs. rclk 0.00 0.00 0.00 ns t rck2rd1 rclk-to-out (pipelined) 12.08 13.76 16.17 ns t rck2rd2 rclk-to-out (non-pipelined) 12.83 14.62 17.18 ns t rclkh rclk minimum high pulse width 0.73 0.73 0.73 ns t rclkl rclk minimum low pulse width 14.41 14.41 14.41 ns t rckp rclk minimum period 15.14 15.14 15.14 ns note: timing data for these sixteen cascaded ram blocks uses a depth of 65,536. for all other combinations, use microsemi?s timing software.
axcelerator family fpgas revision 18 2-95 fifo every memory block has its own embedded fifo contro ller. each fifo block has one read port and one write port. this embedded fifo controller us es no internal fpga logic and features: ? glitch-free fifo flags ? gray-code address counters/pointers to prevent metastability problems ? overflow and underflow control both ports are configurable in various sizes from 4k x 1 to 128 x 36, similar to the ram block size. each port is fully synchronous. read and write operations can be completely independ ent. data on the appropriate wd pins are written to the fifo on every active wclk edge as long as wen is high. data is read from the fifo and output on the appropriate rd pins on every active rclk edge as long as ren is asserted. the fifo block offers programmable almost-empty (aempty) and almost-full (afull) flags as well as empty and full flags ( figure 2-61 ): ? the full flag is synchronous to wclk. it allows the fifo to inhibit writing when full. ? the empty flag is synchronous to rclk. it allo ws the fifo to inhibit reading at the empty condition. gray code counters are used to prevent metastabilit y problems associated with flag logic. the depth of the fifo is dependent on the data wi dth and the number of memory blo cks used to create the fifo. the write operations to the fifo are synchronous with respect to the wclk, and the read operations are synchronous with respect to the rclk. the fifo block may be reset to the empty state. figure 2-61 ? axcelerator ram with embe dded fifo controller cnt 16 e cnt 16 e = = afval aeval > > = sub 16 rclk wd wclk clr fwen fren depth[3:0] rd [n-1:0] wd [n-1:0] rclk wclk ra [j:0] wa [j:0] ren wen full aempty afull empty rd pipe rw[2:0] ww[2:0] width[2:0] ram
detailed specifications 2-96 revision 18 fifo flag logic the fifo is user configurable into various depths and widths. figure 2-62 shows the fifo address counter details. ? bits 11 to 5 are active for all modes. ? as the data word size is reduced, more l east-significant bits are added to the address. ? as the number of cascaded blocks increases, t he number of significant bits in the address increases. for example, if four blocks are cascaded as a 1kx16 fifo with each block having a 1kx4 aspect ratio, bits 11 to 2 of the address will be used to specify lo cations within each ram block, whereas bits 13 and 12 will be used to specify the ram block. the afull and aempty flag threshold values are programmable. the threshold values are afval and aeval, respectively. although the trigger threshold for each flag is defined with eight bits, the effective number of threshold bits in the comparison depend s on the configuration. the effective number of threshold bits corresponds to the range of active bits in the fifo address space ( table 2-94 ). note: inactive counter bits are set to zero. figure 2-62 ? fifo address counters table 2-94 ? fifo flag logic mode inactive aeval/afval bits inactive diff bits (set to 0) diff comparison to afval/aeval non-cascade [7:4] [15:12] diff[11:8] withae/fval[3:0] cascade 2 blocks [7:5] [15:13] diff[12:8] withae/fval[4:0] cascade 4 blocks [7:6] [15:14] diff[13:8] withae/fval[5:0] cascade 8 blocks [7] [15] diff[14:8] withae/fval[6:0] cascade 16 blocks none none diff[15:8] withae/fval[7:0] cntr [12] activate fifo address counters >> ren [4:0], rad [11:0] >> wen [4:0], wad [11:0] [12:w] [13:w] [14:w] [15:w] 128x36 1kx4 512x9 256x18 [11:5] [11:4] [11:3] [11:2] [11:1] [11:0] 4kx1 2kx2 variable active address space cntr [15] activate cntr [2] activate cntr [3] activate cntr [4] activate cntr [11:5] always active cntr [13] activate cntr [14] activate cntr [0] activate cntr [1] activate cas 16 blks by 1 by 2 by 4 by 9 by 18 by 36 cas 2 blks cas 4 blks cas 8 blks mode when active counter bits r/w en[3] r/w add[0] r/w add[1] r/w add[2] r/w add[3] r/w add[7:5] r/w add[11:8] r/w en[0] r/w en[1] r/w en[2] r/w add[4] fifo address aeval/afval[7] not compared not compared not compared not compared not compared not compared aeval/afval[3:0] aeval/afval[4] aeval/afval[5] aeval/afval[6] cntr [15:0] alignment of threshold bits
axcelerator family fpgas revision 18 2-97 figure 2-63 illustrates flag generation. the verilog codes for the flags are: assign af = (diff[15:0] >={afval[7:0],8'b00000000})?1:0; assign ae = ({aeval[7:0],8'b00000000}>=diff[15:0])?1:0; the number of diff-bits active depends on the configuration depth and width ( ta b l e 2 - 9 5 ). the active-high clr pin is used to reset the fifo to the empty state, which sets full and afull low, and empty and aempty high. assuming that the empty flag is not set, new data is read from the fifo when ren is valid on the active edge of the clock. write and read transfer s are described with timing requirements in "timing characteristics" on page 2-100 . figure 2-63 ? almost-empty and almost-full logic table 2-95 ? number of available configuration bits number of blocks block dxw number of aeval/afval bits 1 1x1 4 2 1x2 4 2 2x1 5 4 1x4 4 4 2x2 5 4 4x1 6 8 1x8 4 8 2x4 5 8 4x2 6 8 8x1 7 16 1x16 4 16 2x8 5 16 4x4 6 16 8x2 7 16 16x1 8 almost empty and almost full logic wcntr [15:0] wclk rcntr [15:0] rclk 16 16 x y x y aempty afull x>=y (16 bit) diff [15:0] aeval [7:0], gnd [7:0] (msb....lsb) afval [7:0], gnd [7:0] (msb....lsb)
detailed specifications 2-98 revision 18 glitch elimination an analog filter is added to each fifo cont roller to guarantee glitch-free fifo-flag logic. overflow and underflow control the counter msb keeps track of the difference be tween the read address (ra) and the write address (wa). the empty flag is set when the read and wr ite addresses are equal. to prevent underflow, the write address is double-sampled by the read clock prior to comparison with the read address (part a in figure 2-64 ). to prevent overflow, the read address is double-sampled by the write clock prior to comparison to the write address (part b in figure 2-64 ). fifo configurations unlike the ram, the fifo's write width and read wi dth cannot be specified independently. for the fifo, the write and read widths must be the same. the widt h pins are used to specify one of six allowable word widths, as shown in ta b l e 2 - 9 6 . the depth pins allow ram cells to be cascaded to creat e larger fifos. the four pins allow depths of 2, 4, 8, and 16 to be specified. table 2-86 on page 2-87 describes the fifo depth options for various data width and memory blocks. interface figure 2-65 on page 2-99 shows a logic block diagram of the axcelerator fifo module. cascading fifo blocks fifo blocks can be cascaded to create deeper fifo fu nctions. when building larg er fifo blocks, if the word width can be fractured in a multi-bit fifo, the fractured word configuration is recommended over a cascaded configuration. for example, 256x36 can be co nfigured as two blocks of 256x18. this should be taken into account when building the fifo blocks manually. however, when using smartgen, the user only needs to specify the depth and width of the necessary fifo blocks. smartgen automatically configures these blocks to optimize performance. figure 2-64 ? overflow and underflow control table 2-96 ? fifo width configurations width(2:0) w x d 000 1 x 4k 001 2 x 2k 010 4 x 1k 011 9 x 512 100 18 x 256 101 36 x 128 11x reserved ab = empty wa ra rclk = ful l ra wa wclk
axcelerator family fpgas revision 18 2-99 clock as with ram configuration, the rclk and wclk pins have independent polarity selection. figure 2-65 ? fifo block diagram table 2-97 ? fifo signal description signal direction description wclk input write clock (active either edge). fwen input fifo write enable. when this signal is asserted, the wd bus data is latched into the fifo, and the internal write counters are incremented. wd[n-1:0] input write data bus. the value n is dependent on the ram configuration and can be 1, 2, 4, 9, 18, or 36. full output active high signal indicating th at the fifo is full. when this signal is set, additional write requests are ignored. afull output active high signal indi cating that the fifo is afull. afval input 8-bit input defining th e afull value of the fifo. rclk input read clock (active either edge). fren input fifo read enable. rd[n-1:0] output read data bus. the value n is dependent on the ram configuration and can be 1, 2, 4, 9, 18, or 36. empty output empty flag indicating that th e fifo is empty. when this signal is asserted, attempts to read the fifo will be ignored. aempty output active high signal indicating that the fifo is aempty. aeval input 8-bit input defining the al most-empty value of the fifo. pipe input sets the pipe option on or off. clr input active high clear input. depth input determines the depth of the fi fo and the number of fifos to be cascaded. width input determines the width of the da taword/fifo, and the number of the fifos to be cascaded. depth [3:0] rd [35:0] full empty afull aempty width [2:0] fwen fren pipe rclk wd [35:0] aeval [7:0] afval [7:0] wclk clr
timing characteristics figure 2-66 ? fifo model figure 2-67 ? fifo write timing wd fwen fren rclk wclk rd afull empty aempty full clr t wckp t wsu t whd t ck2xf t clr2xf t clr2hf t wckh t wckl wclk clr wd<35:0>, fwen empty, aempty, afull, full
axcelerator family fpgas revision 18 2-101 figure 2-68 ? fifo read timing rclk clr t rckp t rsu t rhd t rck2rd1 t rck2rd2 t ck2xf t clr2xf t clrhf t rckh t rckl fren empty, aempty, afull, full rd <35:0>
detailed specifications 2-102 revision 18 table 2-98 ? one fifo block worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed units parameter description min. max. min. max. min. max. fifo module timing t wsu write setup 11.40 12.98 15.26 ns t whd write hold 0.22 0.25 0.30 ns t wckh wclk high 0.75 0.75 0.75 ns t wckl wclk low 0.88 0.88 0.88 ns t wckp minimum wclk period 1.63 1.63 1.63 ns t rsu read setup 11.63 13.25 15.58 ns t rhd read hold 0.00 0.00 0.00 ns t rckh rclk high 0.77 0.77 0.77 ns t rckl rclk low 0.93 0.93 0.93 ns t rckp minimum rclk period 1.70 1.70 1.70 ns t clrhf clear high 0.00 0.00 0.00 ns t clr2ff clear-to-flag (empty/full) 1.92 2.18 2.57 ns t clr2af clear-to-flag (aempty/ afull) 4.39 5.00 5.88 ns t ck2ff clock-to-flag (empty/full) 2.13 2.42 2.85 ns t ck2af clock-to-flag (aempty/ afull) 5.04 5.75 6.75 ns t rck2rd1 rclk-to-out (pipelined) 1.32 1.51 1.77 ns t rck2rd2 rclk-to-out (non-pipelined) 2.16 2.46 2.90 ns note: timing data for this single block fifo has a depth of 4,096. for all other combinat ions, use microsemi?s timing software.
axcelerator family fpgas revision 18 2-103 table 2-99 ? two fifo blocks cascaded worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed units parameter description min. max. min. max. min. max. fifo module timing t wsu write setup 13.75 15.66 18.41 ns t whd write hold 0.00 0.00 0.00 ns t wckh wclk high 0.75 0.75 0.75 ns t wckl wclk low 1.76 1.76 1.76 ns t wckp minimum wclk period 2.51 2.51 2.51 ns t rsu read setup 14.33 16.32 19.19 ns t rhd read hold 0.00 0.00 0.00 ns t rckh rclk high 0.73 0.73 0.73 ns t rckl rclk low 1.89 1.89 1.89 ns t rckp minimum rclk period 2.62 2.62 2.62 ns t clrhf clear high 0.00 0.00 0.00 ns t clr2ff clear-to-flag (empty/full) 1.92 2.18 2.57 ns t clr2af clear-to-flag (aempty/afull) 4.39 5.00 5.88 ns t ck2ff clock-to-flag (empty/full) 2.13 2.42 2.85 ns t ck2af clock-to-flag (aempty/afull) 5.04 5.75 6.75 ns t rck2rd1 rclk-to-out (pipelined) 1.43 1.63 1.92 ns t rck2rd2 rclk-to-out (nonpipelined) 2.26 2.58 3.03 ns note: timing data for these two cascaded fifo blocks uses a depth of 8,192. for all other combinations, use microsemi?s timing software.
detailed specifications 2-104 revision 18 table 2-100 ? four fifo blocks cascaded worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed units parameter description min. max. min. max. min. max. fifo module timing t wsu write setup 14.60 16.63 19.55 ns t whd write hold 0.00 0.00 0.00 ns t wckh wclk high 0.75 0.75 0.75 ns t wckl wclk low 2.51 2.51 2.51 ns t wckp minimum wclk period 3.26 3.26 3.26 ns t rsu read setup 15.27 17.39 20.44 ns t rhd read hold 0.00 0.00 0.00 ns t rckh rclk high 0.73 0.73 0.73 ns t rckl rclk low 2.96 2.96 2.96 ns t rckp minimum rclk period 3.69 3.69 3.69 ns t clrhf clear high 0.00 0.00 0.00 ns t clr2ff clear-to-flag (empty/full) 1.92 2.18 2.57 ns t clr2af clear-to-flag (aempty/ afull) 4.39 5.00 5.88 ns t ck2ff clock-to-flag (empty/full) 2.13 2.42 2.85 ns t ck2af clock-to-flag (aempty/afull) 5.04 5.75 6.75 ns t rck2rd1 rclk-to-out (pipelined) 2.36 2.69 3.16 ns t rck2rd2 rclk-to-out (nonpipelined) 2.83 3.23 3.79 ns note: timing data for these four cascaded fifo blocks uses a depth of 16,384. for all other combinations, use microsemi?s timing software.
axcelerator family fpgas revision 18 2-105 table 2-101 ? eight fifo blocks cascaded worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed units parameter description min. max. min. max. min. max. fifo module timing t wsu write setup 15.46 17.61 20.70 ns t whd write hold 0.00 0.00 0.00 ns t wckh wclk high 0.75 0.75 0.75 ns t wckl wclk low 5.13 5.13 5.13 ns t wckp minimum wclk period 5.88 5.88 5.88 ns t rsu read setup 16.22 18.47 21.72 ns t rhd read hold 0.00 0.00 0.00 ns t rckh rclk high 0.73 0.73 0.73 ns t rckl rclk low 5.77 5.77 5.77 ns t rckp minimum rclk period 6.50 6.50 6.50 ns t clrhf clear high 0.00 0.00 0.00 ns t clr2ff clear-to-flag (empty/full) 1.92 2.18 2.57 ns t clr2af clear-to-flag (aempty/afull) 4.39 5.00 5.88 ns t ck2ff clock-to-flag (empty/full) 2.13 2.42 2.85 ns t ck2af clock-to-flag (aempty/afull) 5.04 5.75 6.75 ns t rck2rd1 rclk-to-out (pipelined) 3.39 3.86 4.54 ns t rck2rd2 rclk-to-out (nonpipelined) 4.93 5.62 6.61 ns note: timing data for these eight cascaded fifo blocks uses a depth of 32,768. for all other combinations, use microsemi?s timing software.
detailed specifications 2-106 revision 18 building ram and fifo modules ram and fifo modules can be generated and in cluded in a design in two different ways: ? using the smartgen core generator where th e user defines the depth and width of the fifo/ram, and then instantiates this block into the design (refer to the smartgen, flashrom, analog system builder, and flash memory system builder user?s guide for more information). ? the alternative is to in stantiate the ram/fifo bl ocks manually, using invert ers for polarity control and tying all unused data bits to ground. other architectural features low power mode although designed for high performance, the ax architecture also allows the user to place the device into a low power mode. each i/o bank in an axcelerator device can be configured individually, when in low power mode, to tristate all outputs, disable inputs, or both. the low power mode is activated by asserting the lp pin, which is grounded in normal operation. while in the low power mode, the device is still fully functional and all internal logic states are preserved. this allows a user to disable all but a few signa ls and operate the part in a low-frequency, watchdog table 2-102 ? sixteen fifo blocks cascaded worst-case commercial conditions vcca = 1.425 v, vcci = 3.0 v, t j = 70c ?2 speed ?1 speed std speed units parameter description min. max. min. max. min. max. fifo module timing t wsu write setup 16.32 18.60 21.86 ns t whd write hold 0.00 0.00 0.00 ns t wckh wclk high 0.75 0.75 0.75 ns t wckl wclk low 13.40 13.40 13.40 ns t wckp minimum wclk period 14.15 14.15 14.15 ns t rsu read setup 17.16 19.54 22.97 ns t rhd read hold 0.00 0.00 0.00 ns t rckh rclk high 0.73 0.73 0.73 ns t rckl rclk low 14.41 14.41 14.41 ns t rckp minimum rclk period 15.14 15.14 15.14 ns t clrhf clear high 0.00 0.00 0.00 ns t clr2ff clear-to-flag (empty/full) 1.92 2.18 2.57 ns t clr2af clear-to-flag (aempty/afull) 4.39 5.00 5.88 ns t ck2ff clock-to-flag (empty/full) 2.13 2.42 2.85 ns t ck2af clock-to-flag (aempty/ afull) 5.04 5.75 6.75 ns t rck2rd1 rclk-to-out (pipelined) 12.08 13.76 16.17 ns t rck2rd2 rclk-to-out (nonpipelined) 12.83 14.62 17.18 ns note: timing data for these sixteen cascaded fifo blocks us es a depth of 65,536. for all other combinations, use microsemi?s timing software.
axcelerator family fpgas revision 18 2-107 mode if desired. please note, if the i/o bank is not dis abled, differential i/os belonging to the i/o bank will still consume normal power, even when operating in the low power mode. the axcelerator device will resume normal operation 10 s after the lp pin is pulled low. to further reduce power consumption, the internal charge pump can be bypassed and an external power supply voltage can be used instead. this saves the internal charge- pump operating current, resulting in no dc current draw. the axcelerator family devices have a dedicated "v pump " pin that can be used to access an external charge pump device. in normal ch ip operation, when using the internal charge pump, v pump should be tied to gnd. when the voltage level on v pump is set to 3.3v, the internal charge pump is turned off, and the v pump voltage will be used as the charge pump voltage. adequate voltage regulation (i.e. high drive, low output imped ance, and good decoupling) should be used at v pump . in addition, any pll in use can be powered down to further reduce power consumption. this can be done with the powerdown pin driven low. driving th is pin high restarts the pll with the output clock(s) being stable once lock is restored. jtag axcelerator offers a jtag interface that is complia nt with the ieee 1149.1 standard. the user can employ the jtag interface for probing a design and pe rforming any jtag public instructions as defined in the table 2-103 . interface the interface consists of four inputs: test mode select (tms), test data in (tdi), test clock (tck), tap controller reset (trst), and an output, test data out (tdo). tms, tdi, and trst have on-chip pull-up resistors. trst trst (test-logic reset) is an active-low, asynchronous reset signal to the tap controller. the trst input can be used to reset the test access port (tap) controller to the trst state. the tap controller can be held at this state permanently by grounding the trst pin. to hold the jtag tap controller in the trst state, it is recommended to connect trst to ground via a 1 k resistor. there is an optional internal pull-up resistor availabl e for the trst input that can be set by the user at programming. care should be exercised when using th is option in combination with an external tie-off to ground. an on-chip power-on-reset (powrst) circuit is in cluded. powrst has the same function as "trst," but it only occurs at power-up or during re covery from a vcca and/or vccda voltage drop. table 2-103 ? jtag instruction code instruction (ir4:ir0) binary code extest 00000 preload / sample 00001 intest 00010 usercode 00011 idcode 00100 highz 01110 clamp 01111 diagnostic 10000 reserved all others bypass 11111
detailed specifications 2-108 revision 18 tdo tdo is normally tristated, and it is active only when the tap controller is in the "shift_dr" state or "shift_ir" state. the least significant bit of the selected regist er (i.e. ir or dr) is clocked out to tdo first by the falling edge of tck. tap controller the tap controller is compliant with the ieee standard 1149.1. it is a state machine of 16 states that controls the instruction register (ir) and the data registers (such as bsr, idcode, usrcode, bypass, etc.). the tap controller steps into one of the states depending on the sequence of tms at the rising edges of tck. instruction register (ir) the ir has five bits (ir4 to ir0). at the trst st ate, ir is reset to idcode. each time when ir is selected, it goes through "select ir-scan," "capture-ir," "shift-ir, " all the way through "update-ir." when there is no test error, the first five data bits co ming out of tdo during the "shift-ir" will be "10111". if a test error occurs, the last three bits will contain one to three zeroes corresponding to negatively asserted signals: "tdo_errorb," "proba_errorb," and "probb_ errorb." the error(s) will be erased when the tap is at the "u pdate-ir" or the trst state. when in user mode start-up sequence, if the micro-probe has not been used, the "proba_e rrorb" is used as a "power-up done successfully" flag. data registers (drs) data registers are distributed throughout the chip. they store testing/progra mming vectors. the msb of a data register is connected to tdi, while the lsb is connected to tdo. there are different types of data registers. descriptions of the main registers are as follow: 1. idcode: the idcode is a 20-bit hard coded jtag silicon signature. it is a hardwired device id code, which contains the microsemi identity, part number, and version number in a specific jtag format. 2. usercode: the usercode is a 33-bit programmable register . however, only 20 bits are allocated to use as jtag silicon signature. it is a supplementary id entity code for the user to program information to distinguish different programmed parts. use rcode fuses will read out as "zeroes" when not programmed, so only the "1" bits need to be programmed. 3. boundary-scan register (bsr): each i/o contains three boundary-scan cells. each cell has a shift register bit, a latch, and two muxes. the boundary-scan cells are used for the output-enable (e), outp ut (o), and input (i) registers. the bit order of the boundary-scan ce lls for each of them is e-o-i. the boundary-scan cells are then chained serially to form the boundary-scan register (bsr). the length of the bsr is the number of i/os in the die multiplied by three. 4. bypass register (byr): this is the "1-bit" register. it is used to shorte n the tdi-tdo serial chain in board-level testing to only one bit per device not being tested. it is also selected for all "reserved" or unused instructions. probing internal activities of the jtag interface can be obse rved via the silicon explorer ii probes: "pra," "prb," "prc," and "prd." special fuses security microsemi antifuse fpgas, with fus elock technology, offer the highest level of design security available in a programmable logic device. since antifuse fpgas are live-at power-up, there is no bitstream that can be intercepted, and no bitstr eam or programming data is ever downloaded to the device during power-up, thus protecting again st device cloning. in addition, special security fuses are hidden
axcelerator family fpgas revision 18 2-109 throughout the fabric of the device and may be programmed by the user to thwart attempts to reverse engineer the device by attempting to exploit either th e programming or probing interfaces. both invasive and noninvasive attacks against an axcelerator device that access or bypass these security fuses will destroy access to the rest of the device. (refer to the design security in nonvolatile flash and antifuse fpgas white paper). look for this symbol to ensure your valuable ip is prot ected with highest level of security in the industry. to ensure maximum security in axcelerator devices, it is recommended that t he user program the device security fuse (sfus). when programmed, the silicon explorer ii testing probes are disabled to prevent internal probing, and the programming interface is al so disabled. all jtag public instructions are still accessible by the user. for more informatio n, refer to the implementation of security in actel antifuse fpgas application note. global set fuse the global set fuse determines if all r-cells and i/o registers (inreg, outr eg, and enreg) are either cleared or preset by driving the gclr and gpset inputs of all r-cells and i/o registers ( figure 2-31 on page 2-58 ). default setting is to clear all registers (gclr = 0 and gpset =1) at device power-up. when the gbsetfus option is che cked during fuse file gener ation, all registers are preset (gclr = 1 and gpset= 0). a local clr or preset will take precedenc e over this setting. bo th pins are pulled high during normal device operation. for use details, see the libero ide online help. silicon explorer ii probe interface silicon explorer ii is an integrated hardware and software soluti on that, in conjunction with the designer tools, allows users to examine any of the internal nets (except i/o registers) of the device while it is operating in a prototype or a produc tion system. the user can probe up to four nodes at a time without changing the placement and routing of the design and without using any additional device resources. highlighted nets in designer?s chipplanner can be acce ssed using silicon explorer ii in order to observe their real time values. silicon explorer ii's noninvasive method does not alter timing or loading effects, thus shortening the debug cycle. in addition, sili con explorer ii does not require relayout or additional muxes to bring signals out to external pins, which is necessary when using programmable logic devices from other suppliers. by eliminating multiple place-and-route program cycles, t he integrity of the design is maintained throughout the debug process. each member of the axcelerator family has four ex ternal pads: pra, prb, prc, and prd. these can be used to bring out four probe signals from the axcele rator device (note that the ax125 only has two probe signals that can be observed: pra and prb). each co re tile has up to two probe signals. to disallow probing, the sfus security fuse in the silicon signature has to be programmed (see "special fuses" on page 2-108 ). silicon explorer ii connects to the host pc using a standard serial port connector. connections to the circuit board are achieved using a nine-pin d-sub connector ( figure 1-9 on page 1-7 ). once the design has been placed-and-routed, and the axcelerator dev ice has been programmed, s ilicon explorer ii can be connected and the explorer software can be launched. silicon explorer ii comes with an additional optional pc hosted tool that emul ates an 18-channel logic analyzer. four channels are used to monitor four internal nodes, and 14 channels are available to probe external signals. the software included with the tool provides the user with an intuitive interface that allows for easy viewing and editing of signal waveforms. figure 2-69 ? fuselock logo ? e u
detailed specifications 2-110 revision 18 programming device programming is supported through the silicon sculptor ii, a single-site, robust and compact device programmer for the pc. up to four silicon sc ulptor iis can be daisy-chained and controlled from a single pc host. with standalone software for the pc, silicon sculptor ii is designed to allow concurrent programming of multiple units from the same pc when daisy-chained. silicon sculptor ii progr ams devices independently to achieve th e fastest programming times possible. each fuse is verified by silicon sculptor ii to ensure correct programming. furthermore, at the end of programming, there are integrity te sts that are run to ensure that programming was completed properly. not only does it test programmed and nonprogrammed fuse s, silicon sculptor ii also provides a self-test to test its own hardware extensively. programming an axcelerator device using silicon sculpt or ii is similar to programming any other antifuse device. the procedure is as follows: 1. load the *.afm file. 2. select the device to be programmed. 3. begin programming. when the design is ready to go to production, mi crosemi offers device volume-programming services either through distribution partners or via our in-house programming center. in addition, bp microsystems offers multi-site progra mmers that provide qualified support for axcelerator devices. for more details on programming the axcelerator devices, please refer to the silicon sculptor ii user?s guide .
axcelerator family fpgas revision 18 2-111

revision 18 3-1 3 ? package pin assignments bg729 note for package manufacturing and environmental information, visit resource center at http://www.microsemi.com/soc/pr oducts/rescenter/package/index.html . a1 ball pad corner d f h k m p t v y ad af ag e g j l n r u w ac ae b a c ab aa 1 3 6 8 10 12 14 16 20 24 26 27 18 2 4 7 9 11 13 15 19 23 25 17 22 21 5
package pin assignments 3-2 revision 18 bg729 ax1000 function pin number bank 0 io00nb0f0 e6 io00pb0f0 f6 io01nb0f0 g8 io01pb0f0 g7 io02nb0f0 d7 io02pb0f0 e7 io03nb0f0 d5 io03pb0f0 e5 io04nb0f0 g9 io04pb0f0 h9 io05nb0f0 e8 io05pb0f0 f8 io06nb0f0 c6 io06pb0f0 d6 io07nb0f0 b5 io07pb0f0 c5 io08nb0f0 a6 io08pb0f0 a5 io09nb0f0 e9 io09pb0f0 f9 io10nb0f0 g10 io10pb0f0 h10 io11nb0f0 b7 io11pb0f0 b6 io12nb0f1 c8 io12pb0f1 c7 io13nb0f1 e10 io13pb0f1 f10 io14nb0f1 g11 io14pb0f1 h11 io15nb0f1 d9 io15pb0f1 d8 io16nb0f1 a8 io16pb0f1 a7 io17nb0f1 b9 io17pb0f1 b8 io18nb0f1 c10 io18pb0f1 c9 io19nb0f1 e11 io19pb0f1 f11 io20nb0f1 g12 io20pb0f1 h12 io21nb0f1 d11 io21pb0f1 d10 io22nb0f2 a10 io22pb0f2 a9 io23nb0f2 b11 io23pb0f2 b10 io24nb0f2 g13 io24pb0f2 h13 io25nb0f2 c12 io25pb0f2 c11 io26nb0f2 e12 io26pb0f2 d12 io27nb0f2 e13 io27pb0f2 f13 io28nb0f2 g14 io28pb0f2 h14 io29nb0f2 a12 io29pb0f2 b12 io30nb0f2/hclkan c13 io30pb0f2/hclkap d13 io31nb0f2/hclkbn f14 io31pb0f2/hclkbp e14 bank 1 io32nb1f3/hclkcn c14 io32pb1f3/hclkcp b14 io33nb1f3/hclkdn d16 io33pb1f3/hclkdp d15 io34nb1f3 b16 io34pb1f3 a16 io35nb1f3 e15 io35pb1f3 f15 bg729 ax1000 function pin number io36nb1f3 h15 io36pb1f3 g15 io37nb1f3 c17 io37pb1f3 c16 io38nb1f3 b18 io38pb1f3 b17 io39nb1f3 a18 io39pb1f3 a17 io40nb1f3 h16 io40pb1f3 g16 io41nb1f4 b19 io41pb1f4 a19 io42nb1f4 c19 io42pb1f4 c18 io43nb1f4 d18 io43pb1f4 d17 io44nb1f4 h17 io44pb1f4 g17 io45nb1f4 f17 io45pb1f4 e17 io46nb1f4 b20 io46pb1f4 a20 io47nb1f4 c21 io47pb1f4 c20 io48nb1f4 h18 io48pb1f4 g18 io49nb1f4 f18 io49pb1f4 e18 io50nb1f4 d20 io50pb1f4 d19 io51nb1f4 a22 io51pb1f4 a21 io52nb1f4 b22 io52pb1f4 b21 io53nb1f4 f19 io53pb1f4 e19 io54nb1f5 f20 bg729 ax1000 function pin number
axcelerator family fpgas revision 18 3-3 io54pb1f5 e20 io55nb1f5 e21 io55pb1f5 d21 io56nb1f5 h19 io56pb1f5 g19 io57nb1f5 d22 io57pb1f5 c22 io58nb1f5 b23 io58pb1f5 a23 io59nb1f5 d23 io59pb1f5 c23 io60nb1f5 g21 io60pb1f5 g20 io61nb1f5 e23 io61pb1f5 e22 io62nb1f5 f22 io62pb1f5 f21 io63nb1f5 h20 io63pb1f5 j19 bank 2 io64nb2f6 j21 io64pb2f6 h21 io65nb2f6 f24 io65pb2f6 f23 io66nb2f6 f26 io66pb2f6 f25 io67nb2f6 e26 io67pb2f6 e25 io68nb2f6 j22 io68pb2f6 h22 io69nb2f6 g24 io69pb2f6 g23 io70nb2f6 k20 io70pb2f6 j20 io71nb2f6 g26 io71pb2f6 g25 io72nb2f6 j24 bg729 ax1000 function pin number io72pb2f6 j23 io73nb2f6 h24 io73pb2f6 h23 io74nb2f7 l21 io74pb2f7 k21 io75nb2f7 g27 io75pb2f7 f27 io76nb2f7 k23 io76pb2f7 k22 io77nb2f7 h26 io77pb2f7 h25 io78nb2f7 k25 io78pb2f7 k24 io79nb2f7 j26 io79pb2f7 j25 io80nb2f7 m20 io80pb2f7 l20 io81nb2f7 j27 io81pb2f7 h27 io82nb2f7 l23 io82pb2f7 l22 io83nb2f7 l25 io83pb2f7 l24 io84nb2f7 n21 io84pb2f7 m21 io85nb2f8 k27 io85pb2f8 k26 io86nb2f8 m23 io86pb2f8 m22 io87nb2f8 m25 io87pb2f8 m24 io88nb2f8 l27 io88pb2f8 l26 io89nb2f8 m27 io89pb2f8 m26 io90nb2f8 n23 io90pb2f8 n22 bg729 ax1000 function pin number io91nb2f8 n25 io91pb2f8 n24 io92nb2f8 n27 io92pb2f8 n26 io93nb2f8 p26 io93pb2f8 p27 io94nb2f8 n19 io94pb2f8 n20 io95nb2f8 p23 io95pb2f8 p22 bank 3 io96nb3f9 p25 io96pb3f9 p24 io97nb3f9 r26 io97pb3f9 r27 io98nb3f9 p21 io98pb3f9 p20 io99nb3f9 r24 io99pb3f9 r25 io100nb3f9 t26 io100pb3f9 t27 io101nb3f9 t24 io101pb3f9 t25 io102nb3f9 r20 io102pb3f9 r21 io103nb3f9 r23 io103pb3f9 r22 io104nb3f9 u26 io104pb3f9 u27 io105nb3f9 u24 io105pb3f9 u25 io106nb3f9 r19 io106pb3f9 p19 io107nb3f10 v26 io107pb3f10 v27 io108nb3f10 t23 io108pb3f10 t22 bg729 ax1000 function pin number
package pin assignments 3-4 revision 18 io109nb3f10 v24 io109pb3f10 v25 io110nb3f10 t20 io110pb3f10 t21 io111nb3f10 w26 io111pb3f10 w27 io112nb3f10 u22 io112pb3f10 u23 io113nb3f10 y26 io113pb3f10 y27 io114nb3f10 u20 io114pb3f10 u21 io115nb3f10 w24 io115pb3f10 w25 io116nb3f10 v22 io116pb3f10 v23 io117nb3f10 y24 io117pb3f10 y25 io118nb3f11 v20 io118pb3f11 v21 io119nb3f11 aa26 io119pb3f11 aa27 io120nb3f11 w22 io120pb3f11 w23 io121nb3f11 aa24 io121pb3f11 aa25 io122nb3f11 w20 io122pb3f11 w21 io123nb3f11 ab26 io123pb3f11 ab27 io124nb3f11 y22 io124pb3f11 y23 io125nb3f11 ab24 io125pb3f11 ab25 io126nb3f11 aa22 io126pb3f11 aa23 io127nb3f11 ac26 bg729 ax1000 function pin number io127pb3f11 ac27 io128nb3f11 y20 io128pb3f11 w19 bank 4 io129nb4f12 aa20 io129pb4f12 y21 io130nb4f12 ab22 io130pb4f12 ab23 io131nb4f12 ac22 io131pb4f12 ac23 io132nb4f12 ad23 io132pb4f12 ad24 io133nb4f12 af23 io133pb4f12 ae23 io134nb4f12 ac21 io134pb4f12 ab21 io135nb4f12 ac20 io135pb4f12 ab20 io136nb4f12 ad21 io136pb4f12 ad22 io137nb4f12 y19 io137pb4f12 aa19 io138nb4f12 ae21 io138pb4f12 ae22 io139nb4f13 af21 io139pb4f13 af22 io140nb4f13 ag22 io140pb4f13 ag23 io141nb4f13 y18 io141pb4f13 aa18 io142nb4f13 ae20 io142pb4f13 ad20 io143nb4f13 ag20 io143pb4f13 ag21 io144nb4f13 ac19 io144pb4f13 ab19 io145nb4f13 ad18 bg729 ax1000 function pin number io145pb4f13 ad19 io146nb4f13 ac18 io146pb4f13 ab18 io147nb4f13 y17 io147pb4f13 aa17 io148nb4f13 af19 io148pb4f13 af20 io149nb4f13 ac17 io149pb4f13 ab17 io150nb4f13 ae18 io150pb4f13 ae19 io151nb4f13 aa16 io151pb4f13 y16 io152nb4f14 ag18 io152pb4f14 ag19 io153nb4f14 ac16 io153pb4f14 ab16 io154nb4f14 af17 io154pb4f14 af18 io155nb4f14 ab15 io155pb4f14 ac15 io156nb4f14 ae16 io156pb4f14 ae17 io157nb4f14 y15 io157pb4f14 aa15 io158nb4f14 ag16 io158pb4f14 ag17 io159nb4f14/clken af15 io159pb4f14/clkep af16 io160nb4f14/ clkfn ad14 io160pb4f14/clkfp ad15 bank 5 io161nb5f15/clkgn ae14 io161pb5f15/clkgp ae15 io162nb5f15/clkhn ac13 io162pb5f15/clkhp ad13 io163nb5f15 y14 bg729 ax1000 function pin number
axcelerator family fpgas revision 18 3-5 io163pb5f15 aa14 io164nb5f15 ae13 io164pb5f15 af13 io165nb5f15 af12 io165pb5f15 ag12 io166nb5f15 ad12 io166pb5f15 ae12 io167nb5f15 y13 io167pb5f15 aa13 io168nb5f15 ad11 io168pb5f15 ae11 io169nb5f15 ag11 io169pb5f15 af11 io170nb5f15 ab11 io170pb5f15 ac11 io171nb5f16 af10 io171pb5f16 ag10 io172nb5f16 ad10 io172pb5f16 ae10 io173nb5f16 y12 io173pb5f16 aa12 io174nb5f16 ab10 io174pb5f16 ac10 io175nb5f16 af9 io175pb5f16 ag9 io176nb5f16 ad9 io176pb5f16 ae9 io177nb5f16 y11 io177pb5f16 aa11 io178nb5f16 af8 io178pb5f16 ag8 io179nb5f16 ad8 io179pb5f16 ae8 io180nb5f16 ab9 io180pb5f16 ac9 io181nb5f17 y10 io181pb5f17 aa10 bg729 ax1000 function pin number io182nb5f17 af7 io182pb5f17 ag7 io183nb5f17 ad7 io183pb5f17 ae7 io184nb5f17 ac7 io184pb5f17 ac8 io185nb5f17 af6 io185pb5f17 ag6 io186nb5f17 ab7 io186pb5f17 ab8 io187nb5f17 y9 io187pb5f17 aa9 io188nb5f17 ad6 io188pb5f17 ae6 io189nb5f17 ab6 io189pb5f17 ac6 io190nb5f17 af5 io190pb5f17 ag5 io191nb5f17 aa6 io191pb5f17 aa7 io192nb5f17 y8 io192pb5f17 aa8 bank 6 io193nb6f18 w8 io193pb6f18 y7 io194nb6f18 ab5 io194pb6f18 ac5 io195nb6f18 ac2 io195pb6f18 ac3 io196nb6f18 ac4 io196pb6f18 ad4 io197nb6f18 y5 io197pb6f18 y6 io198nb6f18 ab3 io198pb6f18 ab4 io199nb6f18 v7 io199pb6f18 w7 bg729 ax1000 function pin number io200nb6f18 aa4 io200pb6f18 aa5 io201nb6f18 w5 io201pb6f18 w6 io202nb6f18 ab1 io202pb6f18 ac1 io203nb6f19 y3 io203pb6f19 aa3 io204nb6f19 aa2 io204pb6f19 ab2 io205nb6f19 u8 io205pb6f19 v8 io206nb6f19 v5 io206pb6f19 v6 io207nb6f19 y1 io207pb6f19 aa1 io208nb6f19 w4 io208pb6f19 y4 io209nb6f19 t7 io209pb6f19 u7 io210nb6f19 w2 io210pb6f19 y2 io211nb6f19 u5 io211pb6f19 u6 io212nb6f19 v3 io212pb6f19 w3 io213nb6f19 r9 io213pb6f19 t8 io214nb6f20 u4 io214pb6f20 v4 io215nb6f20 t5 io215pb6f20 t6 io216nb6f20 v1 io216pb6f20 w1 io217nb6f20 r7 io217pb6f20 r8 io218nb6f20 u2 bg729 ax1000 function pin number
package pin assignments 3-6 revision 18 io218pb6f20 v2 io219nb6f20 t1 io219pb6f20 u1 io220nb6f20 r5 io220pb6f20 r6 io221nb6f20 t3 io221pb6f20 t4 io222nb6f20 r2 io222pb6f20 t2 io223nb6f20 p8 io223pb6f20 p9 io224nb6f20 r3 io224pb6f20 r4 bank 7 io225nb7f21 p1 io225pb7f21 r1 io226nb7f21 p3 io226pb7f21 p2 io227nb7f21 n7 io227pb7f21 p7 io228nb7f21 p5 io228pb7f21 p4 io229nb7f21 n2 io229pb7f21 n1 io230nb7f21 n6 io230pb7f21 p6 io231nb7f21 n9 io231pb7f21 n8 io232nb7f21 n4 io232pb7f21 n3 io233nb7f21 m2 io233pb7f21 m1 io234nb7f21 m4 io234pb7f21 m3 io235nb7f21 m5 io235pb7f21 n5 io236nb7f22 l2 bg729 ax1000 function pin number io236pb7f22 l1 io237nb7f22 l4 io237pb7f22 l3 io238nb7f22 l6 io238pb7f22 m6 io239nb7f22 m8 io239pb7f22 m7 io240nb7f22 k2 io240pb7f22 k1 io241nb7f22 k4 io241pb7f22 k3 io242nb7f22 k5 io242pb7f22 l5 io243nb7f22 j2 io243pb7f22 j1 io244nb7f22 j4 io244pb7f22 j3 io245nb7f22 h2 io245pb7f22 h1 io246nb7f22 h4 io246pb7f22 h3 io247nb7f23 l8 io247pb7f23 l7 io248nb7f23 j6 io248pb7f23 k6 io249nb7f23 h5 io249pb7f23 j5 io250nb7f23 g2 io250pb7f23 g1 io251nb7f23 k8 io251pb7f23 k7 io252nb7f23 g4 io252pb7f23 g3 io253nb7f23 f2 io253pb7f23 f1 io254nb7f23 g6 io254pb7f23 h6 bg729 ax1000 function pin number io255nb7f23 f5 io255pb7f23 g5 io256nb7f23 f3 io256pb7f23 f4 io257nb7f23 h7 io257pb7f23 j7 dedicated i/o gnd a1 gnd a2 gnd a25 gnd a26 gnd a27 gnd a3 gnd ac24 gnd ae1 gnd ae2 gnd ae25 gnd ae26 gnd ae27 gnd ae3 gnd ae5 gnd af1 gnd af2 gnd af25 gnd af26 gnd af27 gnd af3 gnd ag1 gnd ag2 gnd ag25 gnd ag26 gnd ag27 gnd ag3 gnd b1 gnd b2 gnd b25 gnd b26 bg729 ax1000 function pin number
axcelerator family fpgas revision 18 3-7 gnd b27 gnd b3 gnd c1 gnd c2 gnd c25 gnd c26 gnd c27 gnd c3 gnd e27 gnd l11 gnd l12 gnd l13 gnd l14 gnd l15 gnd l16 gnd l17 gnd m11 gnd m12 gnd m13 gnd m14 gnd m15 gnd m16 gnd m17 gnd n11 gnd n12 gnd n13 gnd n14 gnd n15 gnd n16 gnd n17 gnd p11 gnd p12 gnd p13 gnd p14 gnd p15 gnd p16 gnd p17 bg729 ax1000 function pin number gnd r11 gnd r12 gnd r13 gnd r14 gnd r15 gnd r16 gnd r17 gnd t11 gnd t12 gnd t13 gnd t14 gnd t15 gnd t16 gnd t17 gnd u11 gnd u12 gnd u13 gnd u14 gnd u15 gnd u16 gnd u17 gnd/lp j8 nc u3 pra j14 prb d14 prc v14 prd ab14 tck e4 tdi d4 tdo j9 tms h8 trst e3 vcca aa21 vcca ad5 vcca e1 vcca g22 vcca k10 bg729 ax1000 function pin number vcca k11 vcca k17 vcca k18 vcca l10 vcca l18 vcca u10 vcca u18 vcca v10 vcca v11 vcca v17 vcca v18 vccpla a13 vccplb j13 vccplc b15 vccpld c15 vccple ag14 vccplf af14 vccplg ab13 vccplh ag13 vccda a11 vccda ab12 vccda ac12 vccda ac25 vccda ad16 vccda ad17 vccda e16 vccda e2 vccda e24 vccda f12 vccda f16 vccda f7 vccda k14 vccda p10 vccda p18 vccda w14 vccda w9 vccib0 a4 bg729 ax1000 function pin number
package pin assignments 3-8 revision 18 vccib0 b4 vccib0 c4 vccib0 j10 vccib0 j11 vccib0 j12 vccib0 k12 vccib0 k13 vccib1 a24 vccib1 b24 vccib1 c24 vccib1 j16 vccib1 j17 vccib1 j18 vccib1 k15 vccib1 k16 vccib2 d25 vccib2 d26 vccib2 d27 vccib2 k19 vccib2 l19 vccib2 m18 vccib2 m19 vccib2 n18 vccib3 ad25 vccib3 ad26 vccib3 ad27 vccib3 r18 vccib3 t18 vccib3 t19 vccib3 u19 vccib3 v19 vccib4 ae24 vccib4 af24 vccib4 ag24 vccib4 v15 vccib4 v16 vccib4 w16 bg729 ax1000 function pin number vccib4 w17 vccib4 w18 vccib5 ae4 vccib5 af4 vccib5 ag4 vccib5 v12 vccib5 v13 vccib5 w10 vccib5 w11 vccib5 w12 vccib6 ad1 vccib6 ad2 vccib6 ad3 vccib6 r10 vccib6 t10 vccib6 t9 vccib6 u9 vccib6 v9 vccib7 d1 vccib7 d2 vccib7 d3 vccib7 k9 vccib7 l9 vccib7 m10 vccib7 m9 vccib7 n10 vcompla b13 vcomplb a14 vcomplc a15 vcompld j15 vcomple ag15 vcomplf w15 vcomplg ac14 vcomplh w13 vpump d24 bg729 ax1000 function pin number
axcelerator family fpgas revision 18 3-9 fg256 note for package manufacturing and environmental information, visit resource center at http://www.microsemi.com/soc/pr oducts/rescenter/package/index.html . 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 c e g j l n r d f h k m p t b a a1 ball pad corner
package pin assignments 3-10 revision 18 fg256-pin fbga ax125 function pin number bank 0 io01nb0f0 b4 io01pb0f0 b3 io03nb0f0 a4 io03pb0f0 a3 io04nb0f0 b6 io04pb0f0 b5 io06nb0f0 a6 io06pb0f0 a5 io07nb0f0/hclkan b8 io07pb0f0/hclkap b7 io08nb0f0/hclkbn a9 io08pb0f0/hclkbp a8 bank 1 io09nb1f1/hclkcn c10 io09pb1f1/hclkcp c9 io10nb1f1/hclkdn b11 io10pb1f1/hclkdp b10 io12nb1f1 a13 io12pb1f1 a12 io13nb1f1 b13 io13pb1f1 b12 io14nb1f1 c12 io14pb1f1 c11 io15nb1f1 a15 io15pb1f1 b14 io16nb1f1 c15 io16pb1f1 c14 io17nb1f1 d13 io17pb1f1 d12 bank 2 io18nb2f2 f13 io18pb2f2 e13 io19nb2f2 f14 io19pb2f2 e14 io20nb2f2 f15 io20pb2f2 e15 io21nb2f2 c16 io21pb2f2 b16 io22nb2f2 h13 io22pb2f2 g13 io23nb2f2 e16 io23pb2f2 d16 io25nb2f2 h15 io25pb2f2 g15 io26nb2f2 h14 io26pb2f2 g14 io27nb2f2 g16 io27pb2f2 f16 io28nb2f2 k15 io28pb2f2 k16 io29nb2f2 j16 io29pb2f2 h16 bank 3 io30nb3f3 k13 io30pb3f3 j13 io31nb3f3 k14 io31pb3f3 j14 io33nb3f3 l15 io33pb3f3 l16 io35nb3f3 p16 io35pb3f3 n16 io36pb3f3 m16 io37nb3f3 p15 io37pb3f3 r16 io39nb3f3 n15 io39pb3f3 m15 io40nb3f3 m13 io40pb3f3 l13 io41nb3f3 m14 fg256-pin fbga ax125 function pin number io41pb3f3 l14 bank 4 io42nb4f4 n12 io42pb4f4 n13 io43nb4f4 t14 io43pb4f4 r14 io44pb4f4 t15 io45nb4f4 r12 io45pb4f4 r13 io46nb4f4 p11 io46pb4f4 p12 io47pb4f4 t11 io48nb4f4 t12 io48pb4f4 t13 io49nb4f4/clken r9 io49pb4f4/clkep r10 io50nb4f4/clkfn t8 io50pb4f4/clkfp t9 bank 5 io51nb5f5/clkgn p7 io51pb5f5/clkgp p8 io52nb5f5/clkhn r6 io52pb5f5/clkhp r7 io54nb5f5 t5 io54pb5f5 t6 io55nb5f5 p5 io55pb5f5 p6 io56nb5f5 t3 io56pb5f5 t4 io57nb5f5 r3 io57pb5f5 r4 io58nb5f5 r1 io58pb5f5 t2 io59nb5f5 n4 io59pb5f5 n5 fg256-pin fbga ax125 function pin number
axcelerator family fpgas revision 18 3-11 bank 6 io60nb6f6 l4 io60pb6f6 m4 io61nb6f6 l3 io61pb6f6 m3 io63nb6f6 p2 io63pb6f6 n2 io64nb6f6 j4 io64pb6f6 k4 io65nb6f6 n1 io65pb6f6 p1 io67nb6f6 l2 io67pb6f6 m2 io69nb6f6 l1 io69pb6f6 m1 io70nb6f6 j3 io70pb6f6 k3 io71nb6f6 j2 io71pb6f6 k2 bank 7 io72nb7f7 j1 io72pb7f7 k1 io73nb7f7 g2 io73pb7f7 h2 io74nb7f7 g3 io74pb7f7 h3 io75nb7f7 e1 io75pb7f7 f1 io76nb7f7 g1 io77nb7f7 e2 io77pb7f7 f2 io78nb7f7 g4 io78pb7f7 h4 io79nb7f7 c1 io79pb7f7 d1 fg256-pin fbga ax125 function pin number io81nb7f7 c2 io81pb7f7 b1 io82nb7f7 d2 io82pb7f7 d3 io83nb7f7 e3 io83pb7f7 f3 dedicated i/o vccda e4 gnd a1 gnd a16 gnd b15 gnd b2 gnd d15 gnd e12 gnd e5 gnd f11 gnd f6 gnd g10 gnd g7 gnd g8 gnd g9 gnd h10 gnd h7 gnd h8 gnd h9 gnd j10 gnd j7 gnd j8 gnd j9 gnd k10 gnd k7 gnd k8 gnd k9 gnd l11 gnd l6 fg256-pin fbga ax125 function pin number gnd m12 gnd m5 gnd p13 gnd p3 gnd r15 gnd r2 gnd t1 gnd t16 gnd/lp d4 nc a11 nc r11 nc r5 pra d8 prb c8 prc n9 prd p9 tck d5 tdi c6 tdo c4 tms c3 trst c5 vcca d14 vcca f10 vcca f4 vcca f7 vcca f8 vcca f9 vcca g11 vcca g6 vcca h11 vcca h6 vcca j11 vcca j6 vcca k11 vcca k6 fg256-pin fbga ax125 function pin number
package pin assignments 3-12 revision 18 vcca l10 vcca l7 vcca l8 vcca l9 vcca n3 vcca p14 vccpla c7 vccplb d6 vccplc a10 vccpld d10 vccple p10 vccplf n11 vccplg t7 vccplh n7 vccda a2 vccda c13 vccda d9 v ccda h1 vccda j15 vccda n14 vccda n8 vccda p4 vccib0 e6 vccib0 e7 vccib0 e8 vccib1 e10 vccib1 e11 vccib1 e9 vccib2 f12 vccib2 g12 vccib2 h12 vccib3 j12 vccib3 k12 vccib3 l12 vccib4 m10 fg256-pin fbga ax125 function pin number vccib4 m11 vccib4 m9 vccib5 m6 vccib5 m7 vccib5 m8 vccib6 j5 vccib6 k5 vccib6 l5 vccib7 f5 vccib7 g5 vccib7 h5 vcompla a7 vcomplb d7 vcomplc b9 vcompld d11 vcomple t10 vcomplf n10 vcomplg r8 vcomplh n6 vpump a14 fg256-pin fbga ax125 function pin number
axcelerator family fpgas revision 18 3-13 fg256 ax250 function pin number bank 0 io01nb0f0 b4 io01pb0f0 b3 io03nb0f0 a4 io03pb0f0 a3 io05nb0f0 b6 io05pb0f0 b5 io07nb0f0 a6 io07pb0f0 a5 io12nb0f0/hclkan b8 io12pb0f0/hclkap b7 io13nb0f0/hclkbn a9 io13pb0f0/hclkbp a8 bank 1 io14nb1f1/hclkcn c10 io14pb1f1/hclkcp c9 io15nb1f1/hclkdn b11 io15pb1f1/hclkdp b10 io17nb1f1 a13 io17pb1f1 a12 io19nb1f1 b13 io19pb1f1 b12 io21nb1f1 c12 io21pb1f1 c11 io23nb1f1 a15 io23pb1f1 b14 io26nb1f1 c15 io26pb1f1 c14 io27nb1f1 d13 io27pb1f1 d12 bank 2 io29nb2f2 f13 io29pb2f2 e13 io30nb2f2 f14 io30pb2f2 e14 io32nb2f2 c16 io32pb2f2 b16 io33nb2f2 f15 io33pb2f2 e15 io35nb2f2 h13 io35pb2f2 g13 io36nb2f2 e16 io36pb2f2 d16 io38nb2f2 h15 io38pb2f2 g15 io39nb2f2 h14 io39pb2f2 g14 io40nb2f2 g16 io40pb2f2 f16 io43nb2f2 k15 io43pb2f2 k16 io44nb2f2 j16 io44pb2f2 h16 bank 3 io45nb3f3 k13 io45pb3f3 j13 io46nb3f3 k14 io46pb3f3 j14 io52nb3f3 l15 io52pb3f3 l16 io54nb3f3 p16 io54pb3f3 n16 io55pb3f3 m16 io56nb3f3 p15 io56pb3f3 r16 io58nb3f3 n15 io58pb3f3 m15 io59nb3f3 m13 io59pb3f3 l13 io61nb3f3 m14 fg256 ax250 function pin number io61pb3f3 l14 bank 4 io62nb4f4 n12 io62pb4f4 n13 io63nb4f4 t14 io63pb4f4 r14 io66pb4f4 t15 io67nb4f4 r12 io67pb4f4 r13 io69nb4f4 p11 io69pb4f4 p12 io70pb4f4 t11 io73nb4f4 t12 io73pb4f4 t13 io74nb4f4/clken r9 io74pb4f4/clkep r10 io75nb4f4/clkfn t8 io75pb4f4/clkfp t9 bank 5 io76nb5f5/clkgn p7 io76pb5f5/clkgp p8 io77nb5f5/clkhn r6 io77pb5f5/clkhp r7 io79nb5f5 t5 io79pb5f5 t6 io81nb5f5 p5 io81pb5f5 p6 io83nb5f5 t3 io83pb5f5 t4 io85nb5f5 r3 io85pb5f5 r4 io88nb5f5 r1 io88pb5f5 t2 io89nb5f5 n4 io89pb5f5 n5 fg256 ax250 function pin number
package pin assignments 3-14 revision 18 bank 6 io91nb6f6 l4 io91pb6f6 m4 io92nb6f6 l3 io92pb6f6 m3 io94nb6f6 p2 io94pb6f6 n2 io97nb6f6 j4 io97pb6f6 k4 io98nb6f6 n1 io98pb6f6 p1 io100nb6f6 l2 io100pb6f6 m2 io102nb6f6 l1 io102pb6f6 m1 io103nb6f6 j3 io103pb6f6 k3 io104nb6f6 j2 io104pb6f6 k2 bank 7 io107nb7f7 j1 io107pb7f7 k1 io108nb7f7 g2 io108pb7f7 h2 io111nb7f7 g3 io111pb7f7 h3 io112nb7f7 e1 io112pb7f7 f1 io113nb7f7 g1 io114nb7f7 e2 io114pb7f7 f2 io115nb7f7 g4 io115pb7f7 h4 io116nb7f7 c1 io116pb7f7 d1 fg256 ax250 function pin number io117nb7f7 c2 io117pb7f7 b1 io118nb7f7 d2 io118pb7f7 d3 io119nb7f7 e3 io119pb7f7 f3 dedicated i/o vccda e4 gnd a1 gnd a16 gnd b15 gnd b2 gnd d15 gnd e12 gnd e5 gnd f11 gnd f6 gnd g10 gnd g7 gnd g8 gnd g9 gnd h10 gnd h7 gnd h8 gnd h9 gnd j10 gnd j7 gnd j8 gnd j9 gnd k10 gnd k7 gnd k8 gnd k9 gnd l11 gnd l6 fg256 ax250 function pin number gnd m12 gnd m5 gnd p13 gnd p3 gnd r15 gnd r2 gnd t1 gnd t16 gnd/lp d4 pra d8 prb c8 prc n9 prd p9 tck d5 tdi c6 tdo c4 tms c3 trst c5 vcca d14 vcca f10 vcca f4 vcca f7 vcca f8 vcca f9 vcca g11 vcca g6 vcca h11 vcca h6 vcca j11 vcca j6 vcca k11 vcca k6 vcca l10 vcca l7 vcca l8 fg256 ax250 function pin number
axcelerator family fpgas revision 18 3-15 vcca l9 vcca n3 vcca p14 vccpla c7 vccplb d6 vccplc a10 vccpld d10 vccple p10 vccplf n11 vccplg t7 vccplh n7 vccda a11 vccda a2 vccda c13 vccda d9 vccda h1 vccda j15 vccda n14 vccda n8 vccda p4 vccda r11 vccda r5 vccib0 e6 vccib0 e7 vccib0 e8 vccib1 e10 vccib1 e11 vccib1 e9 vccib2 f12 vccib2 g12 vccib2 h12 vccib3 j12 vccib3 k12 vccib3 l12 vccib4 m10 fg256 ax250 function pin number vccib4 m11 vccib4 m9 vccib5 m6 vccib5 m7 vccib5 m8 vccib6 j5 vccib6 k5 vccib6 l5 vccib7 f5 vccib7 g5 vccib7 h5 vcompla a7 vcomplb d7 vcomplc b9 vcompld d11 vcomple t10 vcomplf n10 vcomplg r8 vcomplh n6 vpump a14 fg256 ax250 function pin number
package pin assignments 3-16 revision 18 fg324 note for package manufacturing and environmental information, visit resource center at http://www.microsemi.com/soc/pr oducts/rescenter/package/index.html . 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 c e g j l n r d f h k m p t b a 17 18 u v a1 ball pad corner
axcelerator family fpgas revision 18 3-17 fg324 ax125 function pin number bank 0 io00nb0f0 c5 io00pb0f0 c4 io01nb0f0 a3 io01pb0f0 a2 io02nb0f0 c7 io02pb0f0 c6 io03nb0f0 b5 io03pb0f0 b4 io04nb0f0 a5 io04pb0f0 a4 io05nb0f0 a7 io05pb0f0 a6 io06nb0f0 b7 io06pb0f0 b6 io07nb0f0/hclkan c9 io07pb0f0/hclkap c8 io08nb0f0/hclkbn b10 io08pb0f0/hclkbp b9 bank 1 io09nb1f1/hclkcn d11 io09pb1f1/hclkcp d10 io10nb1f1/hclkdn c12 io10pb1f1/hclkdp c11 io11nb1f1 a15 io11pb1f1 a14 io12nb1f1 b14 io12pb1f1 b13 io13nb1f1 a17 io13pb1f1 a16 io14nb1f1 d13 io14pb1f1 d12 io15nb1f1 c14 io15pb1f1 c13 io16nb1f1 b16 io16pb1f1 c15 io17nb1f1 e14 io17pb1f1 e13 bank 2 io18nb2f2 g14 io18pb2f2 f14 io19nb2f2 d16 io19pb2f2 d15 io20nb2f2 c18 io20pb2f2 b18 io21nb2f2 d17 io21pb2f2 c17 io22nb2f2 f17 io22pb2f2 e17 io23nb2f2 g16 io23pb2f2 f16 io24nb2f2 e18 io24pb2f2 d18 io25nb2f2 g18 io25pb2f2 f18 io26nb2f2 h17 io26pb2f2 g17 io27nb2f2 j16 io27pb2f2 h16 io28nb2f2 j18 io28pb2f2 h18 io29nb2f2 k17 io29pb2f2 j17 bank 3 io30nb3f3 n18 io30pb3f3 m18 io31nb3f3 l18 io31pb3f3 k18 io32nb3f3 l16 io32pb3f3 l17 fg324 ax125 function pin number io33nb3f3 r18 io33pb3f3 p18 io34nb3f3 n15 io34pb3f3 m15 io35nb3f3 m16 io35pb3f3 m17 io36nb3f3 p16 io36pb3f3 n16 io37nb3f3 r17 io37pb3f3 p17 io38nb3f3 n14 io38pb3f3 m14 io39nb3f3 u18 io39pb3f3 t18 io40nb3f3 r16 io40pb3f3 t17 io41nb3f3 p13 io41pb3f3 p14 bank 4 io42nb4f4 t13 io42pb4f4 t14 io43nb4f4 u15 io43pb4f4 t15 io44nb4f4 u13 io44pb4f4 u14 io45nb4f4 v15 io45pb4f4 v16 io46nb4f4 v13 io46pb4f4 v14 io47nb4f4 v12 io47pb4f4 u12 io48nb4f4 v10 io48pb4f4 v11 io49nb4f4/clken t10 io49pb4f4/clkep t11 fg324 ax125 function pin number
package pin assignments 3-18 revision 18 io50nb4f4/clkfn u9 io50pb4f4/clkfp u10 bank 5 io51nb5f5/clkgn r8 io51pb5f5/clkgp r9 io52nb5f5/clkhn t7 io52pb5f5/clkhp t8 io53nb5f5 u6 io53pb5f5 u7 io54nb5f5 v8 io54pb5f5 v9 io55nb5f5 v6 io55pb5f5 v7 io56nb5f5 u4 io56pb5f5 u5 io57nb5f5 t4 io57pb5f5 t5 io58nb5f5 v4 io58pb5f5 v5 io59nb5f5 v2 io59pb5f5 v3 bank 6 io60nb6f6 p5 io60pb6f6 p6 io61nb6f6 t2 io61pb6f6 u3 io62nb6f6 t1 io62pb6f6 u1 io63nb6f6 p1 io63pb6f6 r1 io64nb6f6 r3 io64pb6f6 p3 io65nb6f6 p2 io65pb6f6 r2 io66nb6f6 m3 fg324 ax125 function pin number io66pb6f6 n3 io67nb6f6 m2 io67pb6f6 n2 io68nb6f6 m1 io68pb6f6 n1 io69nb6f6 k4 io69pb6f6 l4 io70nb6f6 k1 io70pb6f6 l1 io71nb6f6 k3 io71pb6f6 l3 bank 7 io72nb7f7 h4 io72pb7f7 j4 io73nb7f7 k2 io73pb7f7 l2 io74nb7f7 h2 io74pb7f7 h1 io75nb7f7 h3 io75pb7f7 j3 io76nb7f7 f2 io76pb7f7 g2 io77nb7f7 f1 io77pb7f7 g1 io78nb7f7 d2 io78pb7f7 e2 io79nb7f7 f3 io79pb7f7 g3 io80nb7f7 e3 io80pb7f7 e4 io81nb7f7 d1 io81pb7f7 e1 io82nb7f7 d3 io82pb7f7 c2 io83nb7f7 b1 fg324 ax125 function pin number io83pb7f7 c1 dedicated i/o vccda f5 gnd a1 gnd a18 gnd b17 gnd b2 gnd c16 gnd c3 gnd e16 gnd f13 gnd f6 gnd g12 gnd g7 gnd h10 gnd h11 gnd h8 gnd h9 gnd j10 gnd j11 gnd j8 gnd j9 gnd k10 gnd k11 gnd k8 gnd k9 gnd l10 gnd l11 gnd l8 gnd l9 gnd m12 gnd m7 gnd n13 gnd n6 gnd r14 fg324 ax125 function pin number
axcelerator family fpgas revision 18 3-19 gnd r4 gnd t16 gnd t3 gnd u17 gnd u2 gnd v1 gnd v18 gnd/lp e5 nc a10 nc a11 nc a12 nc a13 nc a8 nc a9 nc b12 nc f15 nc f4 nc g15 nc g4 nc h14 nc h15 nc h5 nc j1 nc j14 nc j15 nc j5 nc k14 nc k15 nc k5 nc l14 nc l15 nc l5 nc m4 nc m5 nc n17 fg324 ax125 function pin number nc n4 nc n5 nc r12 nc r13 nc r6 nc r7 nc t12 nc t6 nc u16 nc v17 pra e9 prb d9 prc p10 prd r10 tck e6 tdi d7 tdo d5 tms d4 trst d6 vcca e15 vcca g10 vcca g11 vcca g5 vcca g8 vcca g9 vcca h12 vcca h7 vcca j12 vcca j7 vcca k12 vcca k7 vcca l12 vcca l7 vcca m10 vcca m11 fg324 ax125 function pin number vcca m8 vcca m9 vcca p4 vcca r15 vccpla d8 vccplb e7 vccplc b11 vccpld e11 vccple r11 vccplf p12 vccplg u8 vccplh p8 vccda b3 vccda d14 vccda e10 vccda j2 vccda k16 vccda p15 vccda p9 vccda r5 vccib0 f7 vccib0 f8 vccib0 f9 vccib1 f10 vccib1 f11 vccib1 f12 vccib2 g13 vccib2 h13 vccib2 j13 vccib3 k13 vccib3 l13 vccib3 m13 vccib4 n10 vccib4 n11 vccib4 n12 fg324 ax125 function pin number
package pin assignments 3-20 revision 18 vccib5 n7 vccib5 n8 vccib5 n9 vccib6 k6 vccib6 l6 vccib6 m6 vccib7 g6 vccib7 h6 vccib7 j6 vcompla b8 vcomplb e8 vcomplc c10 vcompld e12 vcomple u11 vcomplf p11 vcomplg t9 vcomplh p7 vpump b15 fg324 ax125 function pin number
axcelerator family fpgas revision 18 3-21 fg484 note for package manufacturing and environmental information, visit resource center at http://www.microsemi.com/soc/pr oducts/rescenter/package/index.html . a b c d e f g h j k l m n p r t u v w y aa ab 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a1 ball pad corner
package pin assignments 3-22 revision 18 fg484 ax250 function pin number bank 0 io00nb0f0 d7 io00pb0f0 d6 io01nb0f0 e7 io01pb0f0 e6 io02nb0f0 c5 io02pb0f0 c4 io03nb0f0 c7 io03pb0f0 c6 io04nb0f0 e9 io04pb0f0 e8 io05nb0f0 d9 io05pb0f0 d8 io06nb0f0 b7 io06pb0f0 b6 io07nb0f0 c9 io07pb0f0 c8 io08nb0f0 a7 io08pb0f0 a6 io09nb0f0 b9 io09pb0f0 b8 io10nb0f0 a9 io10pb0f0 a8 io11nb0f0 b10 io11pb0f0 a10 io12nb0f0/hclkan e11 io12pb0f0/hclkap e10 io13nb0f0/hclkbn d12 io13pb0f0/hclkbp d11 bank 1 io14nb1f1/hclkcn f13 io14pb1f1/hclkcp f12 io15nb1f1/hclkdn e14 io15pb1f1/hclkdp e13 io16nb1f1 c13 io16pb1f1 c12 io17nb1f1 b14 io17pb1f1 b13 io18nb1f1 a14 io18pb1f1 a13 io19nb1f1 a16 io19pb1f1 a15 io20nb1f1 b16 io20pb1f1 b15 io21nb1f1 c17 io21pb1f1 c16 io22nb1f1 f15 io22pb1f1 f14 io23nb1f1 d16 io23pb1f1 d15 io24nb1f1 e16 io24pb1f1 e15 io25nb1f1 f18 io25pb1f1 f17 io26nb1f1 d18 io26pb1f1 e17 io27nb1f1 g16 io27pb1f1 g15 bank 2 io28nb2f2 f19 io28pb2f2 e19 io29nb2f2 j16 io29pb2f2 h16 io30nb2f2 e20 io30pb2f2 d20 io31nb2f2 j17 io31pb2f2 h17 io32nb2f2 g20 io32pb2f2 f20 io33nb2f2 h19 io33pb2f2 g19 io34nb2f2 e22 fg484 ax250 function pin number io34pb2f2 d22 io35nb2f2 j18 io35pb2f2 h18 io36nb2f2 g21 io36pb2f2 f21 io37nb2f2 k19 io37pb2f2 j19 io38nb2f2 j20 io38pb2f2 h20 io39nb2f2 l16 io39pb2f2 k16 io40nb2f2 j21 io40pb2f2 h21 io41nb2f2 l17 io41pb2f2 k17 io42nb2f2 j22 io42pb2f2 h22 io43nb2f2 l18 io43pb2f2 k18 io44nb2f2 l20 io44pb2f2 k20 bank 3 io45nb3f3 m19 io45pb3f3 l19 io46nb3f3 m21 io46pb3f3 l21 io47nb3f3 n17 io47pb3f3 m17 io48nb3f3 n18 io48pb3f3 n19 io49nb3f3 n16 io49pb3f3 m16 io50nb3f3 n20 io50pb3f3 m20 io51nb3f3 p21 io51pb3f3 n21 fg484 ax250 function pin number
axcelerator family fpgas revision 18 3-23 io52nb3f3 p18 io52pb3f3 p19 io53nb3f3 r20 io53pb3f3 p20 io54nb3f3 t21 io54pb3f3 r21 io55nb3f3 r17 io55pb3f3 p17 io56nb3f3 u20 io56pb3f3 t20 io57nb3f3 t18 io57pb3f3 r18 io58nb3f3 u19 io58pb3f3 t19 io59nb3f3 r16 io59pb3f3 p16 io60nb3f3 w20 io60pb3f3 v20 io61nb3f3 u18 io61pb3f3 v19 bank 4 io62nb4f4 t15 io62pb4f4 t16 io63nb4f4 w17 io63pb4f4 v17 io64nb4f4 v15 io64pb4f4 v16 io65nb4f4 y19 io65pb4f4 w18 io66nb4f4 ab18 io66pb4f4 ab19 io67nb4f4 w15 io67pb4f4 w16 io68nb4f4 u14 io68pb4f4 u15 io69nb4f4 aa16 fg484 ax250 function pin number io69pb4f4 aa17 io70nb4f4 ab14 io70pb4f4 ab15 io71nb4f4 y14 io71pb4f4 w14 io72nb4f4 aa14 io72pb4f4 aa15 io73nb4f4 aa13 io73pb4f4 ab13 io74nb4f4/clken v12 io74pb4f4/clkep v13 io75nb4f4/clkfn w11 io75pb4f4/clkfp w12 bank 5 io76nb5f5/clkgn u10 io76pb5f5/clkgp u11 io77nb5f5/clkhn v9 io77pb5f5/clkhp v10 io78nb5f5 aa9 io78pb5f5 aa10 io79nb5f5 ab9 io79pb5f5 ab10 io80nb5f5 aa7 io80pb5f5 aa8 io81nb5f5 w8 io81pb5f5 w9 io82nb5f5 ab5 io82pb5f5 ab6 io83nb5f5 aa5 io83pb5f5 aa6 io84nb5f5 u8 io84pb5f5 u9 io85nb5f5 y6 io85pb5f5 y7 io86nb5f5 w6 io86pb5f5 w7 fg484 ax250 function pin number io87nb5f5 y4 io87pb5f5 y5 io88nb5f5 v6 io88pb5f5 v7 io89nb5f5 t7 io89pb5f5 t8 bank 6 io90nb6f6 v4 io90pb6f6 w5 io91nb6f6 p7 io91pb6f6 r7 io92nb6f6 u5 io92pb6f6 t5 io93nb6f6 p6 io93pb6f6 r6 io94nb6f6 t4 io94pb6f6 u4 io95nb6f6 p5 io95pb6f6 r5 io96nb6f6 t3 io96pb6f6 u3 io97nb6f6 p3 io97pb6f6 r3 io98nb6f6 r2 io98pb6f6 t2 io99nb6f6 p4 io99pb6f6 r4 io100nb6f6 p1 io100pb6f6 r1 io101nb6f6 m7 io101pb6f6 n7 io102nb6f6 n2 io102pb6f6 p2 io103nb6f6 m6 io103pb6f6 n6 io104nb6f6 m4 fg484 ax250 function pin number
package pin assignments 3-24 revision 18 io104pb6f6 n4 io105nb6f6 m5 io105pb6f6 n5 io106nb6f6 m3 io106pb6f6 n3 bank 7 io107nb7f7 m2 io107pb7f7 n1 io108nb7f7 l3 io108pb7f7 l2 io109nb7f7 k2 io109pb7f7 k1 io110nb7f7 k5 io110pb7f7 l5 io111nb7f7 k6 io111pb7f7 l6 io112nb7f7 k4 io112pb7f7 k3 io113nb7f7 k7 io113pb7f7 l7 io114nb7f7 h1 io114pb7f7 j1 io115nb7f7 h2 io115pb7f7 j2 io116nb7f7 h4 io116pb7f7 j4 io117nb7f7 h5 io117pb7f7 j5 io118nb7f7 f2 io118pb7f7 g2 io119nb7f7 h6 io119pb7f7 j6 io120nb7f7 f1 io120pb7f7 g1 io121nb7f7 f4 io121pb7f7 g4 fg484 ax250 function pin number io122nb7f7 g5 io122pb7f7 g6 io123nb7f7 f5 io123pb7f7 e4 dedicated i/o vccda h7 gnd a1 gnd a11 gnd a12 gnd a2 gnd a21 gnd a22 gnd aa1 gnd aa2 gnd aa21 gnd aa22 gnd ab1 gnd ab11 gnd ab12 gnd ab2 gnd ab21 gnd ab22 gnd b1 gnd b2 gnd b21 gnd b22 gnd c20 gnd c3 gnd d19 gnd d4 gnd e18 gnd e5 gnd g18 gnd h15 gnd h8 gnd j14 fg484 ax250 function pin number gnd j9 gnd k10 gnd k11 gnd k12 gnd k13 gnd l1 gnd l10 gnd l11 gnd l12 gnd l13 gnd l22 gnd m1 gnd m10 gnd m11 gnd m12 gnd m13 gnd m22 gnd n10 gnd n11 gnd n12 gnd n13 gnd p14 gnd p9 gnd r15 gnd r8 gnd u16 gnd u6 gnd v18 gnd v5 gnd w19 gnd w4 gnd y20 gnd y3 gnd/lp g7 nc a17 nc a18 fg484 ax250 function pin number
axcelerator family fpgas revision 18 3-25 nc a19 nc a4 nc a5 nc aa11 nc aa12 nc aa18 nc aa19 nc aa4 nc ab16 nc ab17 nc ab4 nc ab7 nc ab8 nc b11 nc b12 nc b17 nc b18 nc b19 nc b4 nc b5 nc c10 nc c11 nc c14 nc c15 nc c18 nc c19 nc d1 nc d2 nc d21 nc d3 nc e1 nc e2 nc e21 nc e3 nc f22 nc f3 fg484 ax250 function pin number nc g22 nc g3 nc h3 nc j3 nc k21 nc k22 nc n22 nc p22 nc r19 nc r22 nc t1 nc t22 nc u1 nc u2 nc u21 nc u22 nc v1 nc v2 nc v21 nc v22 nc v3 nc w1 nc w2 nc w21 nc w22 nc w3 nc y10 nc y11 nc y12 nc y13 nc y15 nc y16 nc y17 nc y18 nc y8 nc y9 fg484 ax250 function pin number pra g11 prb f11 prc t12 prd u12 tck g8 tdi f9 tdo f7 tms f6 trst f8 vcca g17 vcca j10 vcca j11 vcca j12 vcca j13 vcca j7 vcca k14 vcca k9 vcca l14 vcca l9 vcca m14 vcca m9 vcca n14 vcca n9 vcca p10 vcca p11 vcca p12 vcca p13 vcca t6 vcca u17 vccpla f10 vccplb g9 vccplc d13 vccpld g13 vccple u13 vccplf t14 vccplg w10 fg484 ax250 function pin number
package pin assignments 3-26 revision 18 vccplh t10 vccda d14 vccda d5 vccda f16 vccda g12 vccda l4 vccda m18 vccda t11 vccda t17 vccda u7 vccda v14 vccda v8 vccib0 a3 vccib0 b3 vccib0 h10 vccib0 h11 vccib0 h9 vccib1 a20 vccib1 b20 vccib1 h12 vccib1 h13 vccib1 h14 vccib2 c21 vccib2 c22 vccib2 j15 vccib2 k15 vccib2 l15 vccib3 m15 vccib3 n15 vccib3 p15 vccib3 y21 vccib3 y22 vccib4 aa20 vccib4 ab20 vccib4 r12 vccib4 r13 fg484 ax250 function pin number vccib4 r14 vccib5 aa3 vccib5 ab3 vccib5 r10 vccib5 r11 vccib5 r9 vccib6 m8 vccib6 n8 vccib6 p8 vccib6 y1 vccib6 y2 vccib7 c1 vccib7 c2 vccib7 j8 vccib7 k8 vccib7 l8 vcompla d10 vcomplb g10 vcomplc e12 vcompld g14 vcomple w13 vcomplf t13 vcomplg v11 vcomplh t9 vpump d17 fg484 ax250 function pin number
axcelerator family fpgas revision 18 3-27 fg484 AX500 function pin number bank 0 io00nb0f0 e3 io00pb0f0 d3 io01nb0f0 e7 io01pb0f0 e6 io02nb0f0 c5 io02pb0f0 c4 io03nb0f0 d7 io03pb0f0 d6 io04nb0f0 b5 io04pb0f0 b4 io05nb0f0 c7 io05pb0f0 c6 io06nb0f0 a5 io06pb0f0 a4 io07nb0f0 a7 io07pb0f0 a6 io08nb0f0 b7 io08pb0f0 b6 io10nb0f0 b9 io10pb0f0 b8 io11nb0f0 e9 io11pb0f0 e8 io12nb0f1 d9 io12pb0f1 d8 io13nb0f1 c9 io13pb0f1 c8 io14nb0f1 a9 io14pb0f1 a8 io15nb0f1 b10 io15pb0f1 a10 io16nb0f1 b12 io16pb0f1 b11 io18nb0f1 c13 io18pb0f1 c12 io19nb0f1/hclkan e11 io19pb0f1/hclkap e10 io20nb0f1/hclkbn d12 io20pb0f1/hclkbp d11 bank 1 io21nb1f2/hclkcn f13 io21pb1f2/hclkcp f12 io22nb1f2/hclkdn e14 io22pb1f2/hclkdp e13 io24nb1f2 a14 io24pb1f2 a13 io25nb1f2 b14 io25pb1f2 b13 io26nb1f2 c15 io27nb1f2 a16 io27pb1f2 a15 io28nb1f2 b16 io28pb1f2 b15 io29nb1f2 d16 io29pb1f2 d15 io30nb1f2 a18 io30pb1f2 a17 io31nb1f2 f15 io31pb1f2 f14 io32nb1f3 c17 io32pb1f3 c16 io33nb1f3 e16 io33pb1f3 e15 io34nb1f3 b18 io34pb1f3 b17 io35nb1f3 b19 io35pb1f3 a19 io36nb1f3 c19 io36pb1f3 c18 io37nb1f3 f18 fg484 AX500 function pin number io37pb1f3 f17 io38nb1f3 d18 io38pb1f3 e17 io39nb1f3 e21 io39pb1f3 d21 io40nb1f3 e20 io40pb1f3 d20 io41nb1f3 g16 io41pb1f3 g15 bank 2 io42nb2f4 f19 io42pb2f4 e19 io43nb2f4 j16 io43pb2f4 h16 io44nb2f4 e22 io44pb2f4 d22 io45nb2f4 h19 io45pb2f4 g19 io46nb2f4 g22 io46pb2f4 f22 io47nb2f4 j17 io47pb2f4 h17 io48nb2f4 g20 io48pb2f4 f20 io49nb2f4 j18 io49pb2f4 h18 io50nb2f4 g21 io50pb2f4 f21 io51nb2f4 k19 io51pb2f4 j19 io52nb2f5 j21 io52pb2f5 h21 io53nb2f5 j20 io53pb2f5 h20 io54nb2f5 j22 fg484 AX500 function pin number
package pin assignments 3-28 revision 18 io54pb2f5 h22 io55nb2f5 l17 io55pb2f5 k17 io56nb2f5 k21 io56pb2f5 k22 io58nb2f5 l20 io58pb2f5 k20 io59nb2f5 l18 io59pb2f5 k18 io60nb2f5 m21 io60pb2f5 l21 io61nb2f5 l16 io61pb2f5 k16 io62nb2f5 m19 io62pb2f5 l19 bank 3 io63nb3f6 n16 io63pb3f6 m16 io64nb3f6 p22 io64pb3f6 n22 io65nb3f6 n20 io65pb3f6 m20 io66nb3f6 p21 io66pb3f6 n21 io67nb3f6 n18 io67pb3f6 n19 io68nb3f6 t22 io68pb3f6 r22 io69nb3f6 n17 io69pb3f6 m17 io70nb3f6 t21 io70pb3f6 r21 io71nb3f6 p18 io71pb3f6 p19 io72nb3f6 r20 fg484 AX500 function pin number io72pb3f6 p20 io73pb3f6 r19 io74nb3f7 v21 io74pb3f7 u21 io75nb3f7 v22 io75pb3f7 u22 io76nb3f7 u20 io76pb3f7 t20 io77nb3f7 r17 io77pb3f7 p17 io78nb3f7 w21 io78pb3f7 w22 io79nb3f7 t18 io79pb3f7 r18 io80nb3f7 w20 io80pb3f7 v20 io81nb3f7 u19 io81pb3f7 t19 io82nb3f7 u18 io82pb3f7 v19 io83nb3f7 r16 io83pb3f7 p16 bank 4 io84nb4f8 ab18 io84pb4f8 ab19 io85nb4f8 t15 io85pb4f8 t16 io86nb4f8 aa18 io86pb4f8 aa19 io87nb4f8 w17 io87pb4f8 v17 io88nb4f8 y19 io88pb4f8 w18 io89nb4f8 u14 io89pb4f8 u15 fg484 AX500 function pin number io90nb4f8 y17 io90pb4f8 y18 io91nb4f8 v15 io91pb4f8 v16 io92pb4f8 ab17 io93nb4f8 y15 io93pb4f8 y16 io94nb4f9 aa16 io94pb4f9 aa17 io95nb4f9 ab14 io95pb4f9 ab15 io96nb4f9 w15 io96pb4f9 w16 io97nb4f9 aa13 io97pb4f9 ab13 io98nb4f9 aa14 io98pb4f9 aa15 io100nb4f9 y14 io100pb4f9 w14 io101nb4f9 y12 io101pb4f9 y13 io102nb4f9 aa11 io102pb4f9 aa12 io103nb4f9/clken v12 io103pb4f9/clkep v13 io104nb4f9/clkfn w11 io104pb4f9/clkfp w12 bank 5 io105nb5f10/clkgn u10 io105pb5f10/clkgp u11 io106nb5f10/clkhn v9 io106pb5f10/clkhp v10 io107nb5f10 y10 io107pb5f10 y11 io108nb5f10 aa9 fg484 AX500 function pin number
axcelerator family fpgas revision 18 3-29 io108pb5f10 aa10 io110nb5f10 ab9 io110pb5f10 ab10 io111nb5f10 y8 io111pb5f10 y9 io112nb5f10 ab7 io113nb5f10 w8 io113pb5f10 w9 io114nb5f11 aa7 io114pb5f11 aa8 io115nb5f11 ab5 io115pb5f11 ab6 io116nb5f11 y6 io116pb5f11 y7 io117nb5f11 u8 io117pb5f11 u9 io118nb5f11 aa5 io118pb5f11 aa6 io119nb5f11 aa4 io119pb5f11 ab4 io120nb5f11 y4 io120pb5f11 y5 io121nb5f11 w6 io121pb5f11 w7 io122nb5f11 v3 io122pb5f11 w3 io123nb5f11 t7 io123pb5f11 t8 io124nb5f11 v4 io124pb5f11 w5 io125nb5f11 v6 io125pb5f11 v7 bank 6 io126nb6f12 v2 io126pb6f12 w2 fg484 AX500 function pin number io127nb6f12 p7 io127pb6f12 r7 io128nb6f12 v1 io128pb6f12 w1 io129nb6f12 u5 io129pb6f12 t5 io130nb6f12 t1 io130pb6f12 u1 io131nb6f12 p6 io131pb6f12 r6 io132nb6f12 t4 io132pb6f12 u4 io133nb6f12 u2 io134nb6f12 t3 io134pb6f12 u3 io135nb6f12 p5 io135pb6f12 r5 io136nb6f13 r2 io136pb6f13 t2 io138nb6f13 p4 io138pb6f13 r4 io139nb6f13 n2 io139pb6f13 p2 io140nb6f13 p3 io140pb6f13 r3 io141nb6f13 m6 io141pb6f13 n6 io142nb6f13 p1 io142pb6f13 r1 io143nb6f13 m5 io143pb6f13 n5 io144nb6f13 m4 io144pb6f13 n4 io145nb6f13 m7 io145pb6f13 n7 fg484 AX500 function pin number io146nb6f13 m3 io146pb6f13 n3 bank 7 io147nb7f14 k7 io147pb7f14 l7 io148nb7f14 m2 io148pb7f14 n1 io149nb7f14 k5 io149pb7f14 l5 io150nb7f14 l3 io150pb7f14 l2 io151nb7f14 k6 io151pb7f14 l6 io152nb7f14 k2 io152pb7f14 k1 io153nb7f14 k4 io153pb7f14 k3 io154nb7f14 h3 io154pb7f14 j3 io155nb7f14 h5 io155pb7f14 j5 io156nb7f14 h4 io156pb7f14 j4 io157nb7f14 h2 io157pb7f14 j2 io158nb7f15 h1 io158pb7f15 j1 io159nb7f15 f1 io159pb7f15 g1 io160nb7f15 f2 io160pb7f15 g2 io161nb7f15 h6 io161pb7f15 j6 io162nb7f15 f3 io162pb7f15 g3 fg484 AX500 function pin number
package pin assignments 3-30 revision 18 io163nb7f15 g5 io163pb7f15 g6 io164nb7f15 d1 io164pb7f15 e1 io165nb7f15 f4 io165pb7f15 g4 io166nb7f15 d2 io166pb7f15 e2 io167nb7f15 f5 io167pb7f15 e4 dedicated i/o vccda h7 gnd a1 gnd a11 gnd a12 gnd a2 gnd a21 gnd a22 gnd aa1 gnd aa2 gnd aa21 gnd aa22 gnd ab1 gnd ab11 gnd ab12 gnd ab2 gnd ab21 gnd ab22 gnd b1 gnd b2 gnd b21 gnd b22 gnd c20 gnd c3 gnd d19 fg484 AX500 function pin number gnd d4 gnd e18 gnd e5 gnd g18 gnd h15 gnd h8 gnd j14 gnd j9 gnd k10 gnd k11 gnd k12 gnd k13 gnd l1 gnd l10 gnd l11 gnd l12 gnd l13 gnd l22 gnd m1 gnd m10 gnd m11 gnd m12 gnd m13 gnd m22 gnd n10 gnd n11 gnd n12 gnd n13 gnd p14 gnd p9 gnd r15 gnd r8 gnd u16 gnd u6 gnd v18 fg484 AX500 function pin number gnd v5 gnd w19 gnd w4 gnd y20 gnd y3 gnd/lp g7 nc ab8 nc ab16 nc c10 nc c11 nc c14 pra g11 prb f11 prc t12 prd u12 tck g8 tdi f9 tdo f7 tms f6 trst f8 vcca g17 vcca j10 vcca j11 vcca j12 vcca j13 vcca j7 vcca k14 vcca k9 vcca l14 vcca l9 vcca m14 vcca m9 vcca n14 vcca n9 vcca p10 fg484 AX500 function pin number
axcelerator family fpgas revision 18 3-31 vcca p11 vcca p12 vcca p13 vcca t6 vcca u17 vccpla f10 vccplb g9 vccplc d13 vccpld g13 vccple u13 vccplf t14 vccplg w10 vccplh t10 vccda d14 vccda d5 vccda f16 vccda g12 vccda l4 vccda m18 vccda t11 vccda t17 vccda u7 vccda v14 vccda v8 vccib0 a3 vccib0 b3 vccib0 h10 vccib0 h11 vccib0 h9 vccib1 a20 vccib1 b20 vccib1 h12 vccib1 h13 vccib1 h14 vccib2 c21 fg484 AX500 function pin number vccib2 c22 vccib2 j15 vccib2 k15 vccib2 l15 vccib3 m15 vccib3 n15 vccib3 p15 vccib3 y21 vccib3 y22 vccib4 aa20 vccib4 ab20 vccib4 r12 vccib4 r13 vccib4 r14 vccib5 aa3 vccib5 ab3 vccib5 r10 vccib5 r11 vccib5 r9 vccib6 m8 vccib6 n8 vccib6 p8 vccib6 y1 vccib6 y2 vccib7 c1 vccib7 c2 vccib7 j8 vccib7 k8 vccib7 l8 vcompla d10 vcomplb g10 vcomplc e12 vcompld g14 vcomple w13 vcomplf t13 fg484 AX500 function pin number vcomplg v11 vcomplh t9 vpump d17 fg484 AX500 function pin number
package pin assignments 3-32 revision 18 fg484 ax1000 function pin number bank 0 io01nb0f0 e3 io01pb0f0 d3 io02nb0f0 e7 io02pb0f0 e6 io05nb0f0 d2 io05pb0f0 e2 io06nb0f0 c5 io06pb0f0 c4 io12nb0f1 d7 io12pb0f1 d6 io13nb0f1 b5 io13pb0f1 b4 io14nb0f1 e9 io14pb0f1 e8 io15nb0f1 c7 io15pb0f1 c6 io16nb0f1 a5 io16pb0f1 a4 io17nb0f1 b7 io17pb0f1 b6 io18nb0f1 a7 io18pb0f1 a6 io19nb0f1 c9 io19pb0f1 c8 io20nb0f1 d9 io20pb0f1 d8 io21nb0f1 b9 io21pb0f1 b8 io22nb0f2 a9 io22pb0f2 a8 io23nb0f2 b10 io23pb0f2 a10 io26nb0f2 a14 io26pb0f2 a13 io29nb0f2 b12 io29pb0f2 b11 io30nb0f2/hclkan e11 io30pb0f2/hclkap e10 io31nb0f2/hclkbn d12 io31pb0f2/hclkbp d11 bank 1 io32nb1f3/hclkcn f13 io32pb1f3/hclkcp f12 io33nb1f3/hclkdn e14 io33pb1f3/hclkdp e13 io34nb1f3 c13 io34pb1f3 c12 io37nb1f3 b14 io37pb1f3 b13 io38nb1f3 a16 io38pb1f3 a15 io40nb1f3 c15 io42nb1f4 a18 io42pb1f4 a17 io43nb1f4 b16 io43pb1f4 b15 io44nb1f4 b18 io44pb1f4 b17 io45nb1f4 b19 io45pb1f4 a19 io46nb1f4 c19 io46pb1f4 c18 io48nb1f4 f15 io48pb1f4 f14 io49nb1f4 d16 io49pb1f4 d15 io50nb1f4 c17 io50pb1f4 c16 io51nb1f4 e22 fg484 ax1000 function pin number io51pb1f4 d22 io52nb1f4 e16 io52pb1f4 e15 io57nb1f5 e21 io57pb1f5 d21 io60nb1f5 g16 io60pb1f5 g15 io61nb1f5 d18 io61pb1f5 e17 io63nb1f5 e20 io63pb1f5 d20 bank 2 io64nb2f6 f18 io64pb2f6 f17 io67nb2f6 f19 io67pb2f6 e19 io68nb2f6 j16 io68pb2f6 h16 io70nb2f6 j17 io70pb2f6 h17 io74nb2f7 j18 io74pb2f7 h18 io75nb2f7 g20 io75pb2f7 f20 io79nb2f7 h19 io79pb2f7 g19 io80nb2f7 l16 io80pb2f7 k16 io84nb2f7 l17 io84pb2f7 k17 io85nb2f8 g21 io85pb2f8 f21 io86nb2f8 g22 io86pb2f8 f22 io87nb2f8 j20 fg484 ax1000 function pin number
axcelerator family fpgas revision 18 3-33 io87pb2f8 h20 io88nb2f8 l18 io88pb2f8 k18 io89nb2f8 k19 io89pb2f8 j19 io90nb2f8 j21 io90pb2f8 h21 io91nb2f8 j22 io91pb2f8 h22 io93nb2f8 k21 io93pb2f8 k22 io94nb2f8 l20 io94pb2f8 k20 io95nb2f8 m21 io95pb2f8 l21 bank 3 io96nb3f9 n16 io96pb3f9 m16 io97nb3f9 m19 io97pb3f9 l19 io98nb3f9 p22 io98pb3f9 n22 io99nb3f9 n20 io99pb3f9 m20 io100nb3f9 n17 io100pb3f9 m17 io101nb3f9 p21 io101pb3f9 n21 io103nb3f9 r20 io103pb3f9 p20 io104nb3f9 n18 io104pb3f9 n19 io105nb3f9 t22 io105pb3f9 r22 io106nb3f9 r17 fg484 ax1000 function pin number io106pb3f9 p17 io107nb3f10 t21 io107pb3f10 r21 io110nb3f10 v22 io110pb3f10 u22 io113nb3f10 v21 io113pb3f10 u21 io114nb3f10 p18 io114pb3f10 p19 io116pb3f10 r19 io117nb3f10 u20 io117pb3f10 t20 io118nb3f11 t18 io118pb3f11 r18 io121nb3f11 u19 io121pb3f11 t19 io124nb3f11 r16 io124pb3f11 p16 io127nb3f11 w21 io127pb3f11 w22 bank 4 io129pb4f12 ab17 io132nb4f12 y19 io132pb4f12 w18 io133nb4f12 w17 io133pb4f12 v17 io135nb4f12 t15 io135pb4f12 t16 io138nb4f12 y17 io138pb4f12 y18 io139nb4f13 v15 io139pb4f13 v16 io140nb4f13 u18 io140pb4f13 v19 io142nb4f13 w20 fg484 ax1000 function pin number io142pb4f13 v20 io143nb4f13 w15 io143pb4f13 w16 io144nb4f13 aa18 io144pb4f13 aa19 io145nb4f13 u14 io145pb4f13 u15 io146nb4f13 y15 io146pb4f13 y16 io147nb4f13 ab18 io147pb4f13 ab19 io149nb4f13 y14 io149pb4f13 w14 io150nb4f13 aa16 io150pb4f13 aa17 io152nb4f14 aa14 io152pb4f14 aa15 io154nb4f14 ab14 io154pb4f14 ab15 io155nb4f14 aa13 io155pb4f14 ab13 io158nb4f14 y12 io158pb4f14 y13 io159nb4f14/clken v12 io159pb4f14/clkep v13 io160nb4f14/clkfn w11 io160pb4f14/clkfp w12 bank 5 io161nb5f15/clkgn u10 io161pb5f15/clkgp u11 io162nb5f15/clkhn v9 io162pb5f15/clkhp v10 io163nb5f15 y10 io163pb5f15 y11 io167nb5f15 aa11 fg484 ax1000 function pin number
package pin assignments 3-34 revision 18 io167pb5f15 aa12 io169nb5f15 aa9 io169pb5f15 aa10 io170nb5f15 ab9 io170pb5f15 ab10 io171nb5f16 w8 io171pb5f16 w9 io172nb5f16 y8 io172pb5f16 y9 io173nb5f16 u8 io173pb5f16 u9 io174nb5f16 aa7 io174pb5f16 aa8 io175nb5f16 ab5 io175pb5f16 ab6 io176nb5f16 aa5 io176pb5f16 aa6 io177nb5f16 aa4 io177pb5f16 ab4 io178nb5f16 y6 io178pb5f16 y7 io179nb5f16 t7 io179pb5f16 t8 io180nb5f16 w6 io180pb5f16 w7 io181nb5f17 y4 io181pb5f17 y5 io184nb5f17 ab7 io187nb5f17 v3 io187pb5f17 w3 io188nb5f17 v4 io188pb5f17 w5 io192nb5f17 v6 io192pb5f17 v7 bank 6 fg484 ax1000 function pin number io194nb6f18 v2 io194pb6f18 w2 io195nb6f18 u5 io195pb6f18 t5 io200nb6f18 t4 io200pb6f18 u4 io201nb6f18 p6 io201pb6f18 r6 io203nb6f19 u2 io204nb6f19 t3 io204pb6f19 u3 io205nb6f19 p5 io205pb6f19 r5 io208nb6f19 v1 io208pb6f19 w1 io209nb6f19 p7 io209pb6f19 r7 io212nb6f19 p4 io212pb6f19 r4 io214nb6f20 p3 io214pb6f20 r3 io215nb6f20 m6 io215pb6f20 n6 io216nb6f20 r2 io216pb6f20 t2 io217nb6f20 t1 io217pb6f20 u1 io219nb6f20 m5 io219pb6f20 n5 io220nb6f20 p1 io220pb6f20 r1 io221nb6f20 n2 io221pb6f20 p2 io222nb6f20 m3 io222pb6f20 n3 fg484 ax1000 function pin number io223nb6f20 m7 io223pb6f20 n7 io224nb6f20 m4 io224pb6f20 n4 bank 7 io225nb7f21 m2 io225pb7f21 n1 io226nb7f21 k2 io226pb7f21 k1 io228nb7f21 l3 io228pb7f21 l2 io229nb7f21 k5 io229pb7f21 l5 io230nb7f21 h1 io230pb7f21 j1 io231nb7f21 h2 io231pb7f21 j2 io232nb7f21 k4 io232pb7f21 k3 io233nb7f21 k6 io233pb7f21 l6 io234nb7f21 f1 io234pb7f21 g1 io235nb7f21 f2 io235pb7f21 g2 io236nb7f22 h3 io236pb7f22 j3 io237nb7f22 k7 io237pb7f22 l7 io241nb7f22 h6 io241pb7f22 j6 io242nb7f22 h4 io242pb7f22 j4 io243nb7f22 h5 io243pb7f22 j5 fg484 ax1000 function pin number
axcelerator family fpgas revision 18 3-35 io246nb7f22 f3 io246pb7f22 g3 io250nb7f23 f4 io250pb7f23 g4 io253nb7f23 g5 io253pb7f23 g6 io254nb7f23 d1 io254pb7f23 e1 io257nb7f23 f5 io257pb7f23 e4 dedicated i/o vccda h7 gnd a1 gnd a11 gnd a12 gnd a2 gnd a21 gnd a22 gnd aa1 gnd aa2 gnd aa21 gnd aa22 gnd ab1 gnd ab11 gnd ab12 gnd ab2 gnd ab21 gnd ab22 gnd b1 gnd b2 gnd b21 gnd b22 gnd c20 gnd c3 gnd d19 fg484 ax1000 function pin number gnd d4 gnd e18 gnd e5 gnd g18 gnd h15 gnd h8 gnd j14 gnd j9 gnd k10 gnd k11 gnd k12 gnd k13 gnd l1 gnd l10 gnd l11 gnd l12 gnd l13 gnd l22 gnd m1 gnd m10 gnd m11 gnd m12 gnd m13 gnd m22 gnd n10 gnd n11 gnd n12 gnd n13 gnd p14 gnd p9 gnd r15 gnd r8 gnd u16 gnd u6 gnd v18 fg484 ax1000 function pin number gnd v5 gnd w19 gnd w4 gnd y20 gnd y3 gnd/lp g7 pra g11 prb f11 prc t12 prd u12 tck g8 tdi f9 tdo f7 tms f6 trst f8 vcca g17 vcca j10 vcca j11 vcca j12 vcca j13 vcca j7 vcca k14 vcca k9 vcca l14 vcca l9 vcca m14 vcca m9 vcca n14 vcca n9 vcca p10 vcca p11 vcca p12 vcca p13 vcca t6 vcca u17 fg484 ax1000 function pin number
package pin assignments 3-36 revision 18 vccpla f10 vccplb g9 vccplc d13 vccpld g13 vccple u13 vccplf t14 vccplg w10 vccplh t10 vccda ab16 vccda ab8 vccda c10 vccda c11 vccda c14 vccda d14 vccda d5 vccda f16 vccda g12 vccda l4 vccda m18 vccda t11 vccda t17 vccda u7 vccda v14 vccda v8 vccib0 a3 vccib0 b3 vccib0 h10 vccib0 h11 vccib0 h9 vccib1 a20 vccib1 b20 vccib1 h12 vccib1 h13 vccib1 h14 vccib2 c21 fg484 ax1000 function pin number vccib2 c22 vccib2 j15 vccib2 k15 vccib2 l15 vccib3 m15 vccib3 n15 vccib3 p15 vccib3 y21 vccib3 y22 vccib4 aa20 vccib4 ab20 vccib4 r12 vccib4 r13 vccib4 r14 vccib5 aa3 vccib5 ab3 vccib5 r10 vccib5 r11 vccib5 r9 vccib6 m8 vccib6 n8 vccib6 p8 vccib6 y1 vccib6 y2 vccib7 c1 vccib7 c2 vccib7 j8 vccib7 k8 vccib7 l8 vcompla d10 vcomplb g10 vcomplc e12 vcompld g14 vcomple w13 vcomplf t13 fg484 ax1000 function pin number vcomplg v11 vcomplh t9 vpump d17 fg484 ax1000 function pin number
axcelerator family fpgas revision 18 3-37 fg676 note for package manufacturing and environmental information, visit resource center at http://www.microsemi.com/soc/pr oducts/rescenter/package/index.html . a1 ball pad corner a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
package pin assignments 3-38 revision 18 fg676 AX500 function pin number bank 0 io00nb0f0 f8 io00pb0f0 e8 io01nb0f0 a5 io01pb0f0 a4 io02nb0f0 e7 io02pb0f0 e6 io03nb0f0 d6 io03pb0f0 d5 io04nb0f0 b5 io04pb0f0 c5 io05nb0f0 b6 io05pb0f0 c6 io06nb0f0 c7 io06pb0f0 d7 io07nb0f0 a7 io07pb0f0 a6 io08nb0f0 c8 io08pb0f0 d8 io09nb0f0 f10 io09pb0f0 f9 io10nb0f0 b8 io10pb0f0 b7 io11nb0f0 d10 io11pb0f0 e10 io12nb0f1 b9 io12pb0f1 c9 io13nb0f1 f11 io13pb0f1 g11 io14nb0f1 d11 io14pb0f1 e11 io15nb0f1 b10 io15pb0f1 c10 io16nb0f1 a10 io16pb0f1 a9 io17nb0f1 f12 io17pb0f1 g12 io18nb0f1 c12 io18pb0f1 c11 io19nb0f1/hclkan a12 io19pb0f1/hclkap b12 io20nb0f1/hclkbn c13 io20pb0f1/hclkbp b13 bank 1 io21nb1f2/hclkcn c15 io21pb1f2/hclkcp c14 io22nb1f2/hclkdn a15 io22pb1f2/hclkdp b15 io23nb1f2 f15 io23pb1f2 g15 io24nb1f2 b16 io24pb1f2 a16 io25nb1f2 a18 io25pb1f2 a17 io26nb1f2 d16 io26pb1f2 e16 io27nb1f2 f16 io27pb1f2 g16 io28nb1f2 c18 io28pb1f2 c17 io29nb1f2 b19 io29pb1f2 b18 io30nb1f2 d19 io30pb1f2 c19 io31nb1f2 f17 io31pb1f2 e17 io32nb1f3 b20 io32pb1f3 a20 io33nb1f3 b22 io33pb1f3 b21 fg676 AX500 function pin number io34nb1f3 d20 io34pb1f3 c20 io35nb1f3 d21 io35pb1f3 c21 io36nb1f3 d22 io36pb1f3 c22 io37nb1f3 f19 io37pb1f3 e19 io38nb1f3 b23 io38pb1f3 a23 io39nb1f3 e21 io39pb1f3 e20 io40nb1f3 d23 io40pb1f3 c23 io41nb1f3 d25 io41pb1f3 c25 bank 2 io42nb2f4 g24 io42pb2f4 g23 io43nb2f4 g26 io43pb2f4 f26 io44nb2f4 f25 io44pb2f4 e25 io45nb2f4 j21 io45pb2f4 j22 io46nb2f4 h25 io46pb2f4 g25 io47nb2f4 k23 io47pb2f4 j23 io48nb2f4 j24 io48pb2f4 h24 io49nb2f4 k21 io49pb2f4 k22 io50nb2f4 k25 io50pb2f4 j25 fg676 AX500 function pin number
axcelerator family fpgas revision 18 3-39 io51nb2f4 l20 io51pb2f4 l21 io52nb2f5 k26 io52pb2f5 j26 io53nb2f5 l23 io53pb2f5 l22 io54nb2f5 l24 io54pb2f5 k24 io55nb2f5 m20 io55pb2f5 m21 io56nb2f5 l26 io56pb2f5 l25 io57nb2f5 m23 io57pb2f5 m22 io58nb2f5 m26 io58pb2f5 m25 io59nb2f5 n22 io59pb2f5 n23 io60nb2f5 n24 io60pb2f5 m24 io61nb2f5 n20 io61pb2f5 n21 io62nb2f5 p25 io62pb2f5 n25 bank 3 io63nb3f6 t26 io63pb3f6 r26 io64nb3f6 r24 io64pb3f6 p24 io65nb3f6 p20 io65pb3f6 p21 io66nb3f6 t25 io66pb3f6 r25 io67nb3f6 t23 io67pb3f6 r23 fg676 AX500 function pin number io68nb3f6 v26 io68pb3f6 u26 io69nb3f6 v25 io69pb3f6 u25 io70nb3f6 y25 io70pb3f6 w25 io71nb3f6 w24 io71pb3f6 v24 io72nb3f6 v23 io72pb3f6 u23 io73nb3f6 t21 io73pb3f6 t20 io74nb3f7 aa26 io74pb3f7 y26 io75nb3f7 aa24 io75pb3f7 y24 io76nb3f7 y23 io76pb3f7 w23 io77nb3f7 v21 io77pb3f7 u21 io78nb3f7 ab25 io78pb3f7 aa25 io79nb3f7 ac26 io79pb3f7 ab26 io80nb3f7 ac24 io80pb3f7 ab24 io81nb3f7 ab23 io81pb3f7 aa23 io82nb3f7 aa22 io82pb3f7 y22 io83nb3f7 ae26 io83pb3f7 ad26 bank 4 io84nb4f8 ab21 io84pb4f8 aa21 fg676 AX500 function pin number io85nb4f8 ae23 io85pb4f8 ae24 io86nb4f8 ac21 io86pb4f8 ac22 io87nb4f8 af22 io87pb4f8 af23 io88nb4f8 ad22 io88pb4f8 ad23 io89nb4f8 ac19 io89pb4f8 ac20 io90nb4f8 ae21 io90pb4f8 ae22 io91nb4f8 aa17 io91pb4f8 aa18 io92nb4f8 ad20 io92pb4f8 ad21 io93nb4f8 af20 io93pb4f8 af21 io94nb4f9 ae19 io94pb4f9 ae20 io95nb4f9 ac17 io95pb4f9 ac18 io96nb4f9 ad18 io96pb4f9 ad19 io97nb4f9 aa16 io97pb4f9 y16 io98nb4f9 ae17 io98pb4f9 ae18 io99nb4f9 ac16 io99pb4f9 ab16 io100nb4f9 af17 io100pb4f9 af18 io101nb4f9 aa15 io101pb4f9 y15 io102nb4f9 ac15 fg676 AX500 function pin number
package pin assignments 3-40 revision 18 io102pb4f9 ab15 io103nb4f9/clken ae16 io103pb4f9/clkep af16 io104nb4f9/clkfn ae14 io104pb4f9/clkfp ae15 bank 5 io105nb5f10/clkgn ae12 io105pb5f10/clkgp ae13 io106nb5f10/clkhn ae11 io106pb5f10/clkhp af11 io107nb5f10 y12 io107pb5f10 aa13 io108nb5f10 ac12 io108pb5f10 ab12 io109nb5f10 ac10 io109pb5f10 ac11 io110nb5f10 af9 io110pb5f10 af10 io111nb5f10 y11 io111pb5f10 aa12 io112nb5f10 ae9 io112pb5f10 ae10 io113nb5f10 ac9 io113pb5f10 ad9 io114nb5f11 af6 io114pb5f11 af7 io115nb5f11 aa10 io115pb5f11 ab10 io116nb5f11 ae7 io116pb5f11 ae8 io117nb5f11 ad7 io117pb5f11 ad8 io118nb5f11 ac7 io118pb5f11 ac8 io119nb5f11 ad6 fg676 AX500 function pin number io119pb5f11 ae6 io120nb5f11 ae5 io120pb5f11 af5 io121nb5f11 af4 io121pb5f11 ae4 io122nb5f11 ac5 io122pb5f11 ac6 io123nb5f11 ad4 io123pb5f11 ad5 io124nb5f11 ab6 io124pb5f11 ab7 io125nb5f11 ae3 io125pb5f11 af3 bank 6 io126nb6f12 ab3 io126pb6f12 ac3 io127nb6f12 aa2 io127pb6f12 ab2 io128nb6f12 ac2 io128pb6f12 ad2 io129nb6f12 y1 io129pb6f12 aa1 io130nb6f12 y3 io130pb6f12 aa3 io131nb6f12 u6 io131pb6f12 v6 io132nb6f12 w2 io132pb6f12 y2 io133nb6f12 v4 io133pb6f12 w4 io134nb6f12 v3 io134pb6f12 w3 io135nb6f12 v1 io135pb6f12 v2 io136nb6f13 u4 fg676 AX500 function pin number io136pb6f13 u5 io137nb6f13 t6 io137pb6f13 t7 io138nb6f13 t5 io138pb6f13 t4 io139nb6f13 r6 io139pb6f13 r7 io140nb6f13 t3 io140pb6f13 u3 io141nb6f13 u1 io141pb6f13 u2 io142nb6f13 r2 io142pb6f13 t2 io143nb6f13 p3 io143pb6f13 r3 io144nb6f13 p5 io144pb6f13 p4 io145nb6f13 p6 io145pb6f13 p7 io146nb6f13 r1 io146pb6f13 t1 bank 7 io147nb7f14 n6 io147pb7f14 n7 io148nb7f14 n5 io148pb7f14 n4 io149nb7f14 n2 io149pb7f14 n3 io150nb7f14 l1 io150pb7f14 m1 io151nb7f14 m2 io151pb7f14 m3 io152nb7f14 m5 io152pb7f14 m4 io153nb7f14 m7 fg676 AX500 function pin number
axcelerator family fpgas revision 18 3-41 io153pb7f14 m6 io154nb7f14 k2 io154pb7f14 l2 io155nb7f14 k3 io155pb7f14 l3 io156nb7f14 l5 io156pb7f14 l4 io157nb7f14 l6 io157pb7f14 l7 io158nb7f15 j1 io158pb7f15 k1 io159nb7f15 j4 io159pb7f15 k4 io160nb7f15 h2 io160pb7f15 j2 io161nb7f15 k6 io161pb7f15 k5 io162nb7f15 h3 io162pb7f15 j3 io163nb7f15 g2 io163pb7f15 g1 io164nb7f15 g4 io164pb7f15 h4 io165nb7f15 f3 io165pb7f15 g3 io166nb7f15 e2 io166pb7f15 f2 io167nb7f15 f5 io167pb7f15 g5 dedicated i/o gnd a1 gnd a13 gnd a14 gnd a19 gnd a26 fg676 AX500 function pin number gnd a8 gnd ac23 gnd ac4 gnd ad24 gnd ad3 gnd ae2 gnd ae25 gnd af1 gnd af13 gnd af14 gnd af19 gnd af26 gnd af8 gnd b2 gnd b25 gnd b26 gnd c24 gnd c3 gnd g20 gnd g7 gnd h1 gnd h19 gnd h26 gnd h8 gnd j18 gnd j9 gnd k10 gnd k11 gnd k12 gnd k13 gnd k14 gnd k15 gnd k16 gnd k17 gnd l10 fg676 AX500 function pin number gnd l11 gnd l12 gnd l13 gnd l14 gnd l15 gnd l16 gnd l17 gnd m10 gnd m11 gnd m12 gnd m13 gnd m14 gnd m15 gnd m16 gnd m17 gnd n1 gnd n10 gnd n11 gnd n12 gnd n13 gnd n14 gnd n15 gnd n16 gnd n17 gnd n26 gnd p1 gnd p10 gnd p11 gnd p12 gnd p13 gnd p14 gnd p15 gnd p16 gnd p17 gnd p26 fg676 AX500 function pin number
package pin assignments 3-42 revision 18 gnd r10 gnd r11 gnd r12 gnd r13 gnd r14 gnd r15 gnd r16 gnd r17 gnd t10 gnd t11 gnd t12 gnd t13 gnd t14 gnd t15 gnd t16 gnd t17 gnd u10 gnd u11 gnd u12 gnd u13 gnd u14 gnd u15 gnd u16 gnd u17 gnd v18 gnd v9 gnd w1 gnd w19 gnd w26 gnd w8 gnd y20 gnd y7 gnd/lp c2 nc a11 nc a21 fg676 AX500 function pin number nc a22 nc a24 nc a25 nc aa11 nc aa19 nc aa20 nc aa4 nc aa5 nc aa6 nc aa7 nc aa8 nc aa9 nc ab1 nc ab11 nc ab17 nc ab18 nc ab19 nc ab20 nc ab8 nc ab9 nc ac1 nc ac13 nc ac14 nc ac25 nc ad1 nc ad11 nc ad16 nc ad25 nc ae1 nc af2 nc af25 nc b11 nc b24 nc b4 nc c16 fg676 AX500 function pin number nc c4 nc d1 nc d13 nc d14 nc d17 nc d18 nc d2 nc d26 nc d3 nc d9 nc e1 nc e18 nc e23 nc e24 nc e26 nc e3 nc e4 nc e9 nc f1 nc f18 nc f20 nc f21 nc f22 nc f23 nc f24 nc f4 nc f6 nc f7 nc g21 nc g22 nc h21 nc h22 nc h23 nc h5 nc h6 fg676 AX500 function pin number
axcelerator family fpgas revision 18 3-43 nc j5 nc j6 nc p22 nc r20 nc r21 nc r22 nc r4 nc r5 nc t22 nc t24 nc u22 nc u24 nc v22 nc v5 nc w21 nc w22 nc w5 nc w6 nc y21 nc y4 nc y5 nc y6 pra e13 prb b14 prc y14 prd ad14 tck e5 tdi b3 tdo g6 tms d4 trst a2 vcca ab4 vcca af24 vcca c1 vcca c26 fg676 AX500 function pin number vcca j10 vcca j11 vcca j12 vcca j13 vcca j14 vcca j15 vcca j16 vcca j17 vcca k18 vcca k9 vcca l18 vcca l9 vcca m18 vcca m9 vcca n18 vcca n9 vcca p18 vcca p9 vcca r18 vcca r9 vcca t18 vcca t9 vcca u18 vcca u9 vcca v10 vcca v11 vcca v12 vcca v13 vcca v14 vcca v15 vcca v16 vcca v17 vccda a3 vccda ab22 vccda ab5 fg676 AX500 function pin number vccda ad10 vccda ad13 vccda ad17 vccda b1 vccda b17 vccda d24 vccda e14 vccda p2 vccda p23 vccib0 g10 vccib0 g8 vccib0 g9 vccib0 h10 vccib0 h11 vccib0 h12 vccib0 h13 vccib0 h9 vccib1 g17 vccib1 g18 vccib1 g19 vccib1 h14 vccib1 h15 vccib1 h16 vccib1 h17 vccib1 h18 vccib2 h20 vccib2 j19 vccib2 j20 vccib2 k19 vccib2 k20 vccib2 l19 vccib2 m19 vccib2 n19 vccib3 p19 vccib3 r19 fg676 AX500 function pin number
package pin assignments 3-44 revision 18 vccib3 t19 vccib3 u19 vccib3 u20 vccib3 v19 vccib3 v20 vccib3 w20 vccib4 w14 vccib4 w15 vccib4 w16 vccib4 w17 vccib4 w18 vccib4 y17 vccib4 y18 vccib4 y19 vccib5 w10 vccib5 w11 vccib5 w12 vccib5 w13 vccib5 w9 vccib5 y10 vccib5 y8 vccib5 y9 vccib6 p8 vccib6 r8 vccib6 t8 vccib6 u7 vccib6 u8 vccib6 v7 vccib6 v8 vccib6 w7 vccib7 h7 vccib7 j7 vccib7 j8 vccib7 k7 vccib7 k8 fg676 AX500 function pin number vccib7 l8 vccib7 m8 vccib7 n8 vccpla e12 vccplb f13 vccplc e15 vccpld g14 vccple af15 vccplf aa14 vccplg af12 vccplh ab13 vcompla d12 vcomplb g13 vcomplc d15 vcompld f14 vcomple ad15 vcomplf ab14 vcomplg ad12 vcomplh y13 vpump e22 fg676 AX500 function pin number
axcelerator family fpgas revision 18 3-45 fg676 ax1000 function pin number bank 0 io00nb0f0 b4 io00pb0f0 c4 io02nb0f0 e7 io02pb0f0 e6 io03nb0f0 d6 io03pb0f0 d5 io04nb0f0 b5 io04pb0f0 c5 io05nb0f0 a5 io05pb0f0 a4 io06nb0f0 f7 io06pb0f0 f6 io07nb0f0 b6 io07pb0f0 c6 io08nb0f0 c7 io08pb0f0 d7 io10nb0f0 f8 io10pb0f0 e8 io11nb0f0 a7 io11pb0f0 a6 io12nb0f1 c8 io12pb0f1 d8 io13nb0f1 b8 io13pb0f1 b7 io14nb0f1 d9 io14pb0f1 e9 io16nb0f1 f10 io16pb0f1 f9 io18nb0f1 b9 io18pb0f1 c9 io19nb0f1 a10 io19pb0f1 a9 io20nb0f1 d10 io20pb0f1 e10 io21nb0f1 b10 io21pb0f1 c10 io22nb0f2 f11 io22pb0f2 g11 io24nb0f2 d11 io24pb0f2 e11 io26nb0f2 c12 io26pb0f2 c11 io28nb0f2 f12 io28pb0f2 g12 io30nb0f2/hclkan a12 io30pb0f2/hclkap b12 io31nb0f2/hclkbn c13 io31pb0f2/hclkbp b13 bank 1 io32nb1f3/hclkcn c15 io32pb1f3/hclkcp c14 io33nb1f3/hclkdn a15 io33pb1f3/hclkdp b15 io35nb1f3 b16 io35pb1f3 a16 io36nb1f3 f15 io36pb1f3 g15 io38nb1f3 f16 io38pb1f3 g16 io40nb1f3 a18 io40pb1f3 a17 io41nb1f4 c18 io41pb1f4 c17 io42nb1f4 d16 io42pb1f4 e16 io44nb1f4 d18 io44pb1f4 d17 io45nb1f4 b19 io45pb1f4 b18 io46nb1f4 b20 io46pb1f4 a20 fg676 ax1000 function pin number io48nb1f4 f17 io48pb1f4 e17 io49nb1f4 a22 io49pb1f4 a21 io50nb1f4 e18 io50pb1f4 f18 io51nb1f4 d19 io51pb1f4 c19 io52nb1f4 d20 io52pb1f4 c20 io54nb1f5 b22 io54pb1f5 b21 io55nb1f5 d21 io55pb1f5 c21 io56nb1f5 f19 io56pb1f5 e19 io57nb1f5 b23 io57pb1f5 a23 io58nb1f5 d22 io58pb1f5 c22 io59nb1f5 b24 io59pb1f5 a24 io60nb1f5 e21 io60pb1f5 e20 io62nb1f5 d23 io62pb1f5 c23 io63nb1f5 f21 io63pb1f5 f20 bank 2 io64nb2f6 h21 io64pb2f6 g21 io65nb2f6 g22 io65pb2f6 f22 io66nb2f6 f24 io66pb2f6 f23 io67nb2f6 e24 fg676 ax1000 function pin number
package pin assignments 3-46 revision 18 io67pb2f6 e23 io68nb2f6 h23 io68pb2f6 h22 io69nb2f6 d25 io69pb2f6 c25 io70nb2f6 g24 io70pb2f6 g23 io71nb2f6 f25 io71pb2f6 e25 io72nb2f6 g26 io72pb2f6 f26 io73nb2f6 e26 io73pb2f6 d26 io74nb2f7 j21 io74pb2f7 j22 io75nb2f7 j24 io75pb2f7 h24 io76nb2f7 k23 io76pb2f7 j23 io77nb2f7 h25 io77pb2f7 g25 io78nb2f7 k25 io78pb2f7 j25 io80nb2f7 k21 io80pb2f7 k22 io81nb2f7 k26 io81pb2f7 j26 io82nb2f7 l24 io82pb2f7 k24 io83nb2f7 l23 io83pb2f7 l22 io84nb2f7 l20 io84pb2f7 l21 io86nb2f8 l26 io86pb2f8 l25 io88nb2f8 m23 fg676 ax1000 function pin number io88pb2f8 m22 io89nb2f8 m26 io89pb2f8 m25 io90nb2f8 m20 io90pb2f8 m21 io91nb2f8 n24 io91pb2f8 m24 io92nb2f8 n22 io92pb2f8 n23 io94nb2f8 n20 io94pb2f8 n21 io95nb2f8 p25 io95pb2f8 n25 bank 3 io98nb3f9 p20 io98pb3f9 p21 io99nb3f9 r24 io99pb3f9 p24 io100nb3f9 r22 io100pb3f9 p22 io101nb3f9 t26 io101pb3f9 r26 io102nb3f9 r21 io102pb3f9 r20 io103nb3f9 t25 io103pb3f9 r25 io105nb3f9 v26 io105pb3f9 u26 io106nb3f9 t23 io106pb3f9 r23 io107nb3f10 u24 io107pb3f10 t24 io108nb3f10 u22 io108pb3f10 t22 io109nb3f10 v25 io109pb3f10 u25 fg676 ax1000 function pin number io110nb3f10 t21 io110pb3f10 t20 io112nb3f10 v23 io112pb3f10 u23 io113nb3f10 y25 io113pb3f10 w25 io114nb3f10 v21 io114pb3f10 u21 io115nb3f10 w24 io115pb3f10 v24 io116nb3f10 aa26 io116pb3f10 y26 io118nb3f11 ac26 io118pb3f11 ab26 io119nb3f11 ab25 io119pb3f11 aa25 io120nb3f11 w22 io120pb3f11 v22 io121nb3f11 y23 io121pb3f11 w23 io122nb3f11 aa24 io122pb3f11 y24 io123nb3f11 ae26 io123pb3f11 ad26 io124nb3f11 y21 io124pb3f11 w21 io125nb3f11 ad25 io125pb3f11 ac25 io126nb3f11 ab23 io126pb3f11 aa23 io127nb3f11 ac24 io127pb3f11 ab24 io128nb3f11 aa22 io128pb3f11 y22 bank 4 io129nb4f12 ab21 fg676 ax1000 function pin number
axcelerator family fpgas revision 18 3-47 io129pb4f12 aa21 io131nb4f12 ad22 io131pb4f12 ad23 io132nb4f12 ae23 io132pb4f12 ae24 io133nb4f12 ab20 io133pb4f12 aa20 io134nb4f12 ac21 io134pb4f12 ac22 io135nb4f12 af22 io135pb4f12 af23 io137nb4f12 ab19 io137pb4f12 aa19 io139nb4f13 ac19 io139pb4f13 ac20 io140nb4f13 ae21 io140pb4f13 ae22 io141nb4f13 ad20 io141pb4f13 ad21 io143nb4f13 ab17 io143pb4f13 ab18 io144nb4f13 ae19 io144pb4f13 ae20 io145nb4f13 ac17 io145pb4f13 ac18 io146nb4f13 ad18 io146pb4f13 ad19 io147nb4f13 aa17 io147pb4f13 aa18 io148nb4f13 af20 io148pb4f13 af21 io149nb4f13 aa16 io149pb4f13 y16 io151nb4f13 ac16 io151pb4f13 ab16 io153nb4f14 ae17 fg676 ax1000 function pin number io153pb4f14 ae18 io154nb4f14 af17 io154pb4f14 af18 io155nb4f14 aa15 io155pb4f14 y15 io157nb4f14 ac15 io157pb4f14 ab15 io159nb4f14/clken ae16 io159pb4f14/clkep af16 io160nb4f14/clkfn ae14 io160pb4f14/clkfp ae15 bank 5 io161nb5f15/clkgn ae12 io161pb5f15/clkgp ae13 io162nb5f15/clkhn ae11 io162pb5f15/clkhp af11 io163nb5f15 ac12 io163pb5f15 ab12 io165nb5f15 y12 io165pb5f15 aa13 io167nb5f15 y11 io167pb5f15 aa12 io168nb5f15 af9 io168pb5f15 af10 io169nb5f15 ab11 io169pb5f15 aa11 io171nb5f16 ae9 io171pb5f16 ae10 io173nb5f16 ac10 io173pb5f16 ac11 io174nb5f16 ae7 io174pb5f16 ae8 io175nb5f16 ac9 io175pb5f16 ad9 io176nb5f16 af6 io176pb5f16 af7 fg676 ax1000 function pin number io177nb5f16 aa10 io177pb5f16 ab10 io179nb5f16 ad7 io179pb5f16 ad8 io180nb5f16 ac7 io180pb5f16 ac8 io181nb5f17 aa9 io181pb5f17 ab9 io183nb5f17 ad6 io183pb5f17 ae6 io184nb5f17 ae5 io184pb5f17 af5 io185nb5f17 aa8 io185pb5f17 ab8 io187nb5f17 ac5 io187pb5f17 ac6 io188nb5f17 ad4 io188pb5f17 ad5 io189nb5f17 ab6 io189pb5f17 ab7 io190nb5f17 af4 io190pb5f17 ae4 io191nb5f17 ae3 io191pb5f17 af3 io192nb5f17 aa6 io192pb5f17 aa7 bank 6 io193nb6f18 y5 io193pb6f18 aa5 io194nb6f18 ab3 io194pb6f18 ac3 io195nb6f18 y4 io195pb6f18 aa4 io196nb6f18 ac2 io196pb6f18 ad2 io197nb6f18 w6 fg676 ax1000 function pin number
package pin assignments 3-48 revision 18 io197pb6f18 y6 io198nb6f18 ad1 io198pb6f18 ae1 io199nb6f18 aa2 io199pb6f18 ab2 io200nb6f18 y3 io200pb6f18 aa3 io201nb6f18 v5 io201pb6f18 w5 io202nb6f18 ab1 io202pb6f18 ac1 io203nb6f19 v4 io203pb6f19 w4 io204nb6f19 v3 io204pb6f19 w3 io205nb6f19 u6 io205pb6f19 v6 io206nb6f19 w2 io206pb6f19 y2 io207nb6f19 u4 io207pb6f19 u5 io208nb6f19 y1 io208pb6f19 aa1 io209nb6f19 t6 io209pb6f19 t7 io211nb6f19 t3 io211pb6f19 u3 io212nb6f19 v1 io212pb6f19 v2 io213nb6f19 t5 io213pb6f19 t4 io214nb6f20 u1 io214pb6f20 u2 io215nb6f20 r6 io215pb6f20 r7 io217nb6f20 r5 fg676 ax1000 function pin number io217pb6f20 r4 io218nb6f20 r2 io218pb6f20 t2 io219nb6f20 p3 io219pb6f20 r3 io220nb6f20 r1 io220pb6f20 t1 io221nb6f20 p6 io221pb6f20 p7 io223nb6f20 p5 io223pb6f20 p4 bank 7 io225nb7f21 n5 io225pb7f21 n4 io226nb7f21 n2 io226pb7f21 n3 io227nb7f21 n6 io227pb7f21 n7 io229nb7f21 m7 io229pb7f21 m6 io231nb7f21 m5 io231pb7f21 m4 io232nb7f21 l1 io232pb7f21 m1 io233nb7f21 m2 io233pb7f21 m3 io235nb7f21 k2 io235pb7f21 l2 io236nb7f22 l5 io236pb7f22 l4 io237nb7f22 l6 io237pb7f22 l7 io238nb7f22 k3 io238pb7f22 l3 io240nb7f22 j1 io240pb7f22 k1 fg676 ax1000 function pin number io241nb7f22 k6 io241pb7f22 k5 io242nb7f22 h2 io242pb7f22 j2 io243nb7f22 j4 io243pb7f22 k4 io244nb7f22 h3 io244pb7f22 j3 io245nb7f22 g2 io245pb7f22 g1 io247nb7f23 j6 io247pb7f23 j5 io248nb7f23 e1 io248pb7f23 f1 io249nb7f23 e2 io249pb7f23 f2 io250nb7f23 g4 io250pb7f23 h4 io251nb7f23 f3 io251pb7f23 g3 io253nb7f23 h6 io253pb7f23 h5 io254nb7f23 d2 io254pb7f23 d1 io255nb7f23 e4 io255pb7f23 f4 io256nb7f23 d3 io256pb7f23 e3 io257nb7f23 f5 io257pb7f23 g5 dedicated i/o gnd a1 gnd a13 gnd a14 gnd a19 gnd a26 fg676 ax1000 function pin number
axcelerator family fpgas revision 18 3-49 gnd a8 gnd ac23 gnd ac4 gnd ad24 gnd ad3 gnd ae2 gnd ae25 gnd af1 gnd af13 gnd af14 gnd af19 gnd af26 gnd af8 gnd b2 gnd b25 gnd b26 gnd c24 gnd c3 gnd g20 gnd g7 gnd h1 gnd h19 gnd h26 gnd h8 gnd j18 gnd j9 gnd k10 gnd k11 gnd k12 gnd k13 gnd k14 gnd k15 gnd k16 gnd k17 gnd l10 gnd l11 fg676 ax1000 function pin number gnd l12 gnd l13 gnd l14 gnd l15 gnd l16 gnd l17 gnd m10 gnd m11 gnd m12 gnd m13 gnd m14 gnd m15 gnd m16 gnd m17 gnd n1 gnd n10 gnd n11 gnd n12 gnd n13 gnd n14 gnd n15 gnd n16 gnd n17 gnd n26 gnd p1 gnd p10 gnd p11 gnd p12 gnd p13 gnd p14 gnd p15 gnd p16 gnd p17 gnd p26 gnd r10 gnd r11 fg676 ax1000 function pin number gnd r12 gnd r13 gnd r14 gnd r15 gnd r16 gnd r17 gnd t10 gnd t11 gnd t12 gnd t13 gnd t14 gnd t15 gnd t16 gnd t17 gnd u10 gnd u11 gnd u12 gnd u13 gnd u14 gnd u15 gnd u16 gnd u17 gnd v18 gnd v9 gnd w1 gnd w19 gnd w26 gnd w8 gnd y20 gnd y7 gnd/lp c2 nc a25 nc ac13 nc ac14 nc af2 nc af25 fg676 ax1000 function pin number
package pin assignments 3-50 revision 18 nc d13 nc d14 pra e13 prb b14 prc y14 prd ad14 tck e5 tdi b3 tdo g6 tms d4 trst a2 vcca ab4 vcca af24 vcca c1 vcca c26 vcca j10 vcca j11 vcca j12 vcca j13 vcca j14 vcca j15 vcca j16 vcca j17 vcca k18 vcca k9 vcca l18 vcca l9 vcca m18 vcca m9 vcca n18 vcca n9 vcca p18 vcca p9 vcca r18 vcca r9 vcca t18 fg676 ax1000 function pin number vcca t9 vcca u18 vcca u9 vcca v10 vcca v11 vcca v12 vcca v13 vcca v14 vcca v15 vcca v16 vcca v17 vccpla e12 vccplb f13 vccplc e15 vccpld g14 vccple af15 vccplf aa14 vccplg af12 vccplh ab13 vccda a11 vccda a3 vccda ab22 vccda ab5 vccda ad10 vccda ad11 vccda ad13 vccda ad16 vccda ad17 vccda b1 vccda b11 vccda b17 vccda c16 vccda d24 vccda e14 vccda p2 vccda p23 fg676 ax1000 function pin number vccib0 g10 vccib0 g8 vccib0 g9 vccib0 h10 vccib0 h11 vccib0 h12 vccib0 h13 vccib0 h9 vccib1 g17 vccib1 g18 vccib1 g19 vccib1 h14 vccib1 h15 vccib1 h16 vccib1 h17 vccib1 h18 vccib2 h20 vccib2 j19 vccib2 j20 vccib2 k19 vccib2 k20 vccib2 l19 vccib2 m19 vccib2 n19 vccib3 p19 vccib3 r19 vccib3 t19 vccib3 u19 vccib3 u20 vccib3 v19 vccib3 v20 vccib3 w20 vccib4 w14 vccib4 w15 vccib4 w16 vccib4 w17 fg676 ax1000 function pin number
axcelerator family fpgas revision 18 3-51 vccib4 w18 vccib4 y17 vccib4 y18 vccib4 y19 vccib5 w10 vccib5 w11 vccib5 w12 vccib5 w13 vccib5 w9 vccib5 y10 vccib5 y8 vccib5 y9 vccib6 p8 vccib6 r8 vccib6 t8 vccib6 u7 vccib6 u8 vccib6 v7 vccib6 v8 vccib6 w7 vccib7 h7 vccib7 j7 vccib7 j8 vccib7 k7 vccib7 k8 vccib7 l8 vccib7 m8 vccib7 n8 vcompla d12 vcomplb g13 vcomplc d15 vcompld f14 vcomple ad15 vcomplf ab14 vcomplg ad12 fg676 ax1000 function pin number vcomplh y13 vpump e22 fg676 ax1000 function pin number
package pin assignments 3-52 revision 18 fg896 note for package manufacturing and environmental information, visit resource center at http://www.microsemi.com/soc/pr oducts/rescenter/package/index.html . a1 ball pad corner a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 ag ah aj ak
axcelerator family fpgas revision 18 3-53 fg896 ax1000 function pin number bank 0 io00nb0f0 d6 io00pb0f0 e6 io01nb0f0 a5 io01pb0f0 b5 io02nb0f0 g9 io02pb0f0 g8 io03nb0f0 f8 io03pb0f0 f7 io04nb0f0 d7 io04pb0f0 e7 io05nb0f0 c7 io05pb0f0 c6 io06nb0f0 h9 io06pb0f0 h8 io07nb0f0 d8 io07pb0f0 e8 io08nb0f0 e9 io08pb0f0 f9 io09nb0f0 a7 io09pb0f0 b7 io10nb0f0 h10 io10pb0f0 g10 io11nb0f0 c9 io11pb0f0 c8 io12nb0f1 e10 io12pb0f1 f10 io13nb0f1 d10 io13pb0f1 d9 io14nb0f1 f11 io14pb0f1 g11 io15nb0f1 a10 io15pb0f1 a9 io16nb0f1 h12 io16pb0f1 h11 io17nb0f1 b11 io17pb0f1 b10 io18nb0f1 d11 io18pb0f1 e11 io19nb0f1 c12 io19pb0f1 c11 io20nb0f1 f12 io20pb0f1 g12 io21nb0f1 d12 io21pb0f1 e12 io22nb0f2 h13 io22pb0f2 j13 io23nb0f2 a12 io23pb0f2 a11 io24nb0f2 f13 io24pb0f2 g13 io25nb0f2 b13 io25pb0f2 b12 io26nb0f2 e14 io26pb0f2 e13 io27nb0f2 b14 io27pb0f2 a14 io28nb0f2 h14 io28pb0f2 j14 io29nb0f2 b15 io29pb0f2 a15 io30nb0f2/hclkan c14 io30pb0f2/hclkap d14 io31nb0f2/hclkbn e15 io31pb0f2/hclkbp d15 bank 1 io32nb1f3/hclkcn e17 io32pb1f3/hclkcp e16 io33nb1f3/hclkdn c17 io33pb1f3/hclkdp d17 fg896 ax1000 function pin number io34nb1f3 a17 io34pb1f3 b17 io35nb1f3 d18 io35pb1f3 c18 io36nb1f3 h17 io36pb1f3 j17 io37nb1f3 b19 io37pb1f3 a19 io38nb1f3 h18 io38pb1f3 j18 io39nb1f3 b20 io39pb1f3 a20 io40nb1f3 c20 io40pb1f3 c19 io41nb1f4 e20 io41pb1f4 e19 io42nb1f4 f18 io42pb1f4 g18 io43nb1f4 a22 io43pb1f4 a21 io44nb1f4 f20 io44pb1f4 f19 io45nb1f4 d21 io45pb1f4 d20 io46nb1f4 d22 io46pb1f4 c22 io47nb1f4 a25 io47pb1f4 a24 io48nb1f4 h19 io48pb1f4 g19 io49nb1f4 c24 io49pb1f4 c23 io50nb1f4 g20 io50pb1f4 h20 io51nb1f4 f21 fg896 ax1000 function pin number
package pin assignments 3-54 revision 18 io51pb1f4 e21 io52nb1f4 f22 io52pb1f4 e22 io53nb1f4 b25 io53pb1f4 b24 io54nb1f5 d24 io54pb1f5 d23 io55nb1f5 f23 io55pb1f5 e23 io56nb1f5 h21 io56pb1f5 g21 io57nb1f5 d25 io57pb1f5 c25 io58nb1f5 f24 io58pb1f5 e24 io59nb1f5 d26 io59pb1f5 c26 io60nb1f5 g23 io60pb1f5 g22 io61nb1f5 b27 io61pb1f5 a27 io62nb1f5 f25 io62pb1f5 e25 io63nb1f5 h23 io63pb1f5 h22 bank 2 io64nb2f6 k23 io64pb2f6 j23 io65nb2f6 j24 io65pb2f6 h24 io66nb2f6 h26 io66pb2f6 h25 io67nb2f6 g26 io67pb2f6 g25 io68nb2f6 k25 fg896 ax1000 function pin number io68pb2f6 k24 io69nb2f6 f27 io69pb2f6 e27 io70nb2f6 j26 io70pb2f6 j25 io71nb2f6 h27 io71pb2f6 g27 io72nb2f6 j28 io72pb2f6 h28 io73nb2f6 g28 io73pb2f6 f28 io74nb2f7 l23 io74pb2f7 l24 io75nb2f7 l26 io75pb2f7 k26 io76nb2f7 m25 io76pb2f7 l25 io77nb2f7 k27 io77pb2f7 j27 io78nb2f7 m27 io78pb2f7 l27 io79nb2f7 k30 io79pb2f7 k29 io80nb2f7 m23 io80pb2f7 m24 io81nb2f7 m28 io81pb2f7 l28 io82nb2f7 n26 io82pb2f7 m26 io83nb2f7 n25 io83pb2f7 n24 io84nb2f7 n22 io84pb2f7 n23 io85nb2f8 m29 io85pb2f8 l29 fg896 ax1000 function pin number io86nb2f8 n28 io86pb2f8 n27 io87nb2f8 p29 io87pb2f8 p30 io88nb2f8 p25 io88pb2f8 p24 io89nb2f8 p28 io89pb2f8 p27 io90nb2f8 p22 io90pb2f8 p23 io91nb2f8 r26 io91pb2f8 p26 io92nb2f8 r24 io92pb2f8 r25 io93nb2f8 r29 io93pb2f8 r30 io94nb2f8 r22 io94pb2f8 r23 io95nb2f8 t27 io95pb2f8 r27 bank 3 io96nb3f9 t29 io96pb3f9 t30 io97nb3f9 u29 io97pb3f9 u30 io98nb3f9 t22 io98pb3f9 t23 io99nb3f9 u26 io99pb3f9 t26 io100nb3f9 u24 io100pb3f9 t24 io101nb3f9 v28 io101pb3f9 u28 io102nb3f9 u23 io102pb3f9 u22 fg896 ax1000 function pin number
axcelerator family fpgas revision 18 3-55 io103nb3f9 v27 io103pb3f9 u27 io104nb3f9 w29 io104pb3f9 v29 io105nb3f9 y28 io105pb3f9 w28 io106nb3f9 v25 io106pb3f9 u25 io107nb3f10 w26 io107pb3f10 v26 io108nb3f10 w24 io108pb3f10 v24 io109nb3f10 y27 io109pb3f10 w27 io110nb3f10 v23 io110pb3f10 v22 io111nb3f10 aa29 io111pb3f10 y29 io112nb3f10 y25 io112pb3f10 w25 io113nb3f10 ab27 io113pb3f10 aa27 io114nb3f10 y23 io114pb3f10 w23 io115nb3f10 aa26 io115pb3f10 y26 io116nb3f10 ac28 io116pb3f10 ab28 io117nb3f10 ae29 io117pb3f10 ad29 io118nb3f11 ae28 io118pb3f11 ad28 io119nb3f11 ad27 io119pb3f11 ac27 io120nb3f11 aa24 fg896 ax1000 function pin number io120pb3f11 y24 io121nb3f11 ab25 io121pb3f11 aa25 io122nb3f11 ac26 io122pb3f11 ab26 io123nb3f11 ag28 io123pb3f11 af28 io124nb3f11 ab23 io124pb3f11 aa23 io125nb3f11 af27 io125pb3f11 ae27 io126nb3f11 ad25 io126pb3f11 ac25 io127nb3f11 ae26 io127pb3f11 ad26 io128nb3f11 ac24 io128pb3f11 ab24 bank 4 io129nb4f12 ad23 io129pb4f12 ac23 io130nb4f12 ak26 io130pb4f12 ak27 io131nb4f12 af24 io131pb4f12 af25 io132nb4f12 ag25 io132pb4f12 ag26 io133nb4f12 ad22 io133pb4f12 ac22 io134nb4f12 ae23 io134pb4f12 ae24 io135nb4f12 ah24 io135pb4f12 ah25 io136nb4f12 aj25 io136pb4f12 aj26 io137nb4f12 ad21 fg896 ax1000 function pin number io137pb4f12 ac21 io138nb4f12 ak24 io138pb4f12 ak25 io139nb4f13 ae21 io139pb4f13 ae22 io140nb4f13 ag23 io140pb4f13 ag24 io141nb4f13 af22 io141pb4f13 af23 io142nb4f13 aj23 io142pb4f13 aj24 io143nb4f13 ad19 io143pb4f13 ad20 io144nb4f13 ag21 io144pb4f13 ag22 io145nb4f13 ae19 io145pb4f13 ae20 io146nb4f13 af20 io146pb4f13 af21 io147nb4f13 ac19 io147pb4f13 ac20 io148nb4f13 ah22 io148pb4f13 ah23 io149nb4f13 ac18 io149pb4f13 ab18 io150nb4f13 ak21 io150pb4f13 aj21 io151nb4f13 ae18 io151pb4f13 ad18 io152nb4f14 aj20 io152pb4f14 ak20 io153nb4f14 ag19 io153pb4f14 ag20 io154nb4f14 ah19 io154pb4f14 ah20 fg896 ax1000 function pin number
package pin assignments 3-56 revision 18 io155nb4f14 ac17 io155pb4f14 ab17 io156nb4f14 ak19 io156pb4f14 aj19 io157nb4f14 ae17 io157pb4f14 ad17 io158nb4f14 aj17 io158pb4f14 aj18 io159nb4f14/clken ag18 io159pb4f14/clkep ah18 io160nb4f14/clkfn ag16 io160pb4f14/clkfp ag17 bank 5 io161nb5f15/clkgn ag14 io161pb5f15/clkgp ag15 io162nb5f15/clkhn ag13 io162pb5f15/clkhp ah13 io163nb5f15 ae14 io163pb5f15 ad14 io164nb5f15 aj12 io164pb5f15 aj13 io165nb5f15 ab14 io165pb5f15 ac15 io166nb5f15 ak11 io166pb5f15 ak12 io167nb5f15 ab13 io167pb5f15 ac14 io168nb5f15 ah11 io168pb5f15 ah12 io169nb5f15 ad13 io169pb5f15 ac13 io170nb5f15 aj10 io170pb5f15 aj11 io171nb5f16 ag11 io171pb5f16 ag12 fg896 ax1000 function pin number io172nb5f16 ak9 io172pb5f16 ak10 io173nb5f16 ae12 io173pb5f16 ae13 io174nb5f16 ag9 io174pb5f16 ag10 io175nb5f16 ae11 io175pb5f16 af11 io176nb5f16 ah8 io176pb5f16 ah9 io177nb5f16 ac12 io177pb5f16 ad12 io178nb5f16 aj7 io178pb5f16 aj8 io179nb5f16 af9 io179pb5f16 af10 io180nb5f16 ae9 io180pb5f16 ae10 io181nb5f17 ac11 io181pb5f17 ad11 io182nb5f17 ak6 io182pb5f17 ak7 io183nb5f17 af8 io183pb5f17 ag8 io184nb5f17 ag7 io184pb5f17 ah7 io185nb5f17 ac10 io185pb5f17 ad10 io186nb5f17 aj5 io186pb5f17 aj6 io187nb5f17 ae7 io187pb5f17 ae8 io188nb5f17 af6 io188pb5f17 af7 io189nb5f17 ad8 fg896 ax1000 function pin number io189pb5f17 ad9 io190nb5f17 ah6 io190pb5f17 ag6 io191nb5f17 ag5 io191pb5f17 ah5 io192nb5f17 ac8 io192pb5f17 ac9 bank 6 io193nb6f18 ab7 io193pb6f18 ac7 io194nb6f18 ad5 io194pb6f18 ae5 io195nb6f18 ab6 io195pb6f18 ac6 io196nb6f18 ae4 io196pb6f18 af4 io197nb6f18 aa8 io197pb6f18 ab8 io198nb6f18 af3 io198pb6f18 ag3 io199nb6f18 ac4 io199pb6f18 ad4 io200nb6f18 ab5 io200pb6f18 ac5 io201nb6f18 y7 io201pb6f18 aa7 io202nb6f18 ad3 io202pb6f18 ae3 io203nb6f19 y6 io203pb6f19 aa6 io204nb6f19 y5 io204pb6f19 aa5 io205nb6f19 w8 io205pb6f19 y8 io206nb6f19 aa4 fg896 ax1000 function pin number
axcelerator family fpgas revision 18 3-57 io206pb6f19 ab4 io207nb6f19 w6 io207pb6f19 w7 io208nb6f19 ab3 io208pb6f19 ac3 io209nb6f19 v8 io209pb6f19 v9 io210nb6f19 aa2 io210pb6f19 aa1 io211nb6f19 v5 io211pb6f19 w5 io212nb6f19 y3 io212pb6f19 y4 io213nb6f19 v7 io213pb6f19 v6 io214nb6f20 w3 io214pb6f20 w4 io215nb6f20 u8 io215pb6f20 u9 io216nb6f20 w1 io216pb6f20 w2 io217nb6f20 u7 io217pb6f20 u6 io218nb6f20 u4 io218pb6f20 v4 io219nb6f20 t5 io219pb6f20 u5 io220nb6f20 u3 io220pb6f20 v3 io221nb6f20 t8 io221pb6f20 t9 io222nb6f20 u2 io222pb6f20 v2 io223nb6f20 t7 io223pb6f20 t6 fg896 ax1000 function pin number io224nb6f20 r2 io224pb6f20 t2 bank 7 io225nb7f21 r7 io225pb7f21 r6 io226nb7f21 r4 io226pb7f21 r5 io227nb7f21 r8 io227pb7f21 r9 io228nb7f21 p1 io228pb7f21 r1 io229nb7f21 p9 io229pb7f21 p8 io230nb7f21 n2 io230pb7f21 p2 io231nb7f21 p7 io231pb7f21 p6 io232nb7f21 n3 io232pb7f21 p3 io233nb7f21 p4 io233pb7f21 p5 io234nb7f21 l1 io234pb7f21 m1 io235nb7f21 m4 io235pb7f21 n4 io236nb7f22 n7 io236pb7f22 n6 io237nb7f22 n8 io237pb7f22 n9 io238nb7f22 m5 io238pb7f22 n5 io239nb7f22 l2 io239pb7f22 m2 io240nb7f22 l3 io240pb7f22 m3 fg896 ax1000 function pin number io241nb7f22 m8 io241pb7f22 m7 io242nb7f22 k4 io242pb7f22 l4 io243nb7f22 l6 io243pb7f22 m6 io244nb7f22 k5 io244pb7f22 l5 io245nb7f22 j4 io245pb7f22 j3 io246nb7f22 g2 io246pb7f22 h2 io247nb7f23 l8 io247pb7f23 l7 io248nb7f23 g3 io248pb7f23 h3 io249nb7f23 g4 io249pb7f23 h4 io250nb7f23 j6 io250pb7f23 k6 io251nb7f23 h5 io251pb7f23 j5 io252nb7f23 f2 io252pb7f23 f1 io253nb7f23 k8 io253pb7f23 k7 io254nb7f23 f4 io254pb7f23 f3 io255nb7f23 g6 io255pb7f23 h6 io256nb7f23 f5 io256pb7f23 g5 io257nb7f23 h7 io257pb7f23 j7 dedicated i/o fg896 ax1000 function pin number
package pin assignments 3-58 revision 18 gnd a13 gnd a18 gnd a2 gnd a23 gnd a29 gnd a8 gnd aa10 gnd aa21 gnd aa28 gnd aa3 gnd ab2 gnd ab22 gnd ab29 gnd ab9 gnd ac1 gnd ac30 gnd ae25 gnd ae6 gnd af26 gnd af5 gnd ag27 gnd ag4 gnd ah10 gnd ah15 gnd ah16 gnd ah21 gnd ah28 gnd ah3 gnd aj1 gnd aj2 gnd aj22 gnd aj29 gnd aj30 gnd aj9 gnd ak13 fg896 ax1000 function pin number gnd ak18 gnd ak2 gnd ak23 gnd ak29 gnd ak8 gnd b1 gnd b2 gnd b22 gnd b29 gnd b30 gnd b9 gnd c10 gnd c15 gnd c16 gnd c21 gnd c28 gnd c3 gnd d27 gnd d28 gnd d4 gnd e26 gnd e5 gnd h1 gnd h30 gnd j2 gnd j22 gnd j29 gnd j9 gnd k10 gnd k21 gnd k28 gnd k3 gnd l11 gnd l20 gnd m12 fg896 ax1000 function pin number gnd m13 gnd m14 gnd m15 gnd m16 gnd m17 gnd m18 gnd m19 gnd n1 gnd n12 gnd n13 gnd n14 gnd n15 gnd n16 gnd n17 gnd n18 gnd n19 gnd n30 gnd p12 gnd p13 gnd p14 gnd p15 gnd p16 gnd p17 gnd p18 gnd p19 gnd r12 gnd r13 gnd r14 gnd r15 gnd r16 gnd r17 gnd r18 gnd r19 gnd r28 gnd r3 fg896 ax1000 function pin number
axcelerator family fpgas revision 18 3-59 gnd t12 gnd t13 gnd t14 gnd t15 gnd t16 gnd t17 gnd t18 gnd t19 gnd t28 gnd t3 gnd u12 gnd u13 gnd u14 gnd u15 gnd u16 gnd u17 gnd u18 gnd u19 gnd v1 gnd v12 gnd v13 gnd v14 gnd v15 gnd v16 gnd v17 gnd v18 gnd v19 gnd v30 gnd w12 gnd w13 gnd w14 gnd w15 gnd w16 gnd w17 gnd w18 fg896 ax1000 function pin number gnd w19 gnd y11 gnd y20 gnd/lp e4 nc a16 nc a26 nc a4 nc a6 nc aa30 nc ab1 nc ab30 nc ac2 nc ac29 nc ad1 nc ad2 nc ad30 nc ae1 nc ae15 nc ae16 nc ae2 nc ae30 nc af1 nc af2 nc af29 nc af30 nc ag1 nc ag2 nc ag29 nc ag30 nc ah27 nc ah4 nc aj14 nc aj15 nc aj16 nc aj27 fg896 ax1000 function pin number nc aj4 nc ak14 nc ak15 nc ak16 nc ak17 nc ak22 nc ak4 nc ak5 nc b16 nc b18 nc b21 nc b23 nc b26 nc b4 nc b6 nc b8 nc c27 nc d1 nc d2 nc d29 nc d30 nc e1 nc e2 nc e29 nc e30 nc f15 nc f16 nc f29 nc f30 nc g1 nc g29 nc g30 nc h29 nc j1 nc j30 fg896 ax1000 function pin number
package pin assignments 3-60 revision 18 nc k1 nc k2 nc l30 nc m30 nc n29 nc t1 nc u1 nc w30 nc y1 nc y2 nc y30 pra g15 prb d16 prc ab16 prd af16 tck g7 tdi d5 tdo j8 tms f6 trst c4 vcca ad6 vcca ah26 vcca e28 vcca e3 vcca l12 vcca l13 vcca l14 vcca l15 vcca l16 vcca l17 vcca l18 vcca l19 vcca m11 vcca m20 vcca n11 fg896 ax1000 function pin number vcca n20 vcca p11 vcca p20 vcca r11 vcca r20 vcca t11 vcca t20 vcca u11 vcca u20 vcca v11 vcca v20 vcca w11 vcca w20 vcca y12 vcca y13 vcca y14 vcca y15 vcca y16 vcca y17 vcca y18 vcca y19 vccpla g14 vccplb h15 vccplc g17 vccpld j16 vccple ah17 vccplf ac16 vccplg ah14 vccplh ad15 vccda ad24 vccda ad7 vccda af12 vccda af13 vccda af15 vccda af18 fg896 ax1000 function pin number vccda af19 vccda c13 vccda c5 vccda d13 vccda d19 vccda d3 vccda e18 vccda f26 vccda g16 vccda t25 vccda t4 vccib0 a3 vccib0 b3 vccib0 j10 vccib0 j11 vccib0 j12 vccib0 k11 vccib0 k12 vccib0 k13 vccib0 k14 vccib0 k15 vccib1 a28 vccib1 b28 vccib1 j19 vccib1 j20 vccib1 j21 vccib1 k16 vccib1 k17 vccib1 k18 vccib1 k19 vccib1 k20 vccib2 c29 vccib2 c30 vccib2 k22 vccib2 l21 fg896 ax1000 function pin number
axcelerator family fpgas revision 18 3-61 vccib2 l22 vccib2 m21 vccib2 m22 vccib2 n21 vccib2 p21 vccib2 r21 vccib3 aa22 vccib3 ah29 vccib3 ah30 vccib3 t21 vccib3 u21 vccib3 v21 vccib3 w21 vccib3 w22 vccib3 y21 vccib3 y22 vccib4 aa16 vccib4 aa17 vccib4 aa18 vccib4 aa19 vccib4 aa20 vccib4 ab19 vccib4 ab20 vccib4 ab21 vccib4 aj28 vccib4 ak28 vccib5 aa11 vccib5 aa12 vccib5 aa13 vccib5 aa14 vccib5 aa15 vccib5 ab10 vccib5 ab11 vccib5 ab12 vccib5 aj3 fg896 ax1000 function pin number vccib5 ak3 vccib6 aa9 vccib6 ah1 vccib6 ah2 vccib6 t10 vccib6 u10 vccib6 v10 vccib6 w10 vccib6 w9 vccib6 y10 vccib6 y9 vccib7 c1 vccib7 c2 vccib7 k9 vccib7 l10 vccib7 l9 vccib7 m10 vccib7 m9 vccib7 n10 vccib7 p10 vccib7 r10 vcompla f14 vcomplb j15 vcomplc f17 vcompld h16 vcomple af17 vcomplf ad16 vcomplg af14 vcomplh ab15 vpump g24 fg896 ax1000 function pin number
package pin assignments 3-62 revision 18 fg896 ax2000 function pin number bank 0 io00nb0f0 b4 io00pb0f0 a4 io01nb0f0 f8 io01pb0f0 f7 io02nb0f0 d6 io02pb0f0 e6 io04nb0f0 a5 io04pb0f0 b5 io05nb0f0 h8 io05pb0f0 g8 io06nb0f0 d7 io06pb0f0 e7 io07nb0f0 d8 io07pb0f0 e8 io08nb0f0 c7 io08pb0f0 c6 io09nb0f0 g9 io09pb0f0 h9 io10nb0f0 a6 io10pb0f0 b6 io11nb0f0 h10 io11pb0f0 g10 io12nb0f1 e9 io12pb0f1 f9 io13nb0f1 e10 io13pb0f1 f10 io15nb0f1 f11 io15pb0f1 g11 io16nb0f1 a7 io16pb0f1 b7 io17nb0f1 d10 io17pb0f1 d9 io18nb0f1 c9 io18pb0f1 c8 io19nb0f1 d11 io19pb0f1 e11 io20pb0f1 b8 io21nb0f1 h12 io21pb0f1 h11 io23nb0f2 a10 io23pb0f2 a9 io25nb0f2 f12 io25pb0f2 g12 io26nb0f2 b11 io26pb0f2 b10 io27nb0f2 d12 io27pb0f2 e12 io28nb0f2 c12 io28pb0f2 c11 io30nb0f2 a12 io30pb0f2 a11 io31nb0f2 f13 io31pb0f2 g13 io33nb0f2 h13 io33pb0f2 j13 io34nb0f3 b13 io34pb0f3 b12 io37nb0f3 e14 io37pb0f3 e13 io38nb0f3 b14 io38pb0f3 a14 io39nb0f3 h14 io39pb0f3 j14 io40nb0f3 b15 io40pb0f3 a15 io41nb0f3/hclkan c14 io41pb0f3/hclkap d14 io42nb0f3/hclkbn e15 io42pb0f3/hclkbp d15 fg896 ax2000 function pin number bank 1 io43nb1f4/hclkcn e17 io43pb1f4/hclkcp e16 io44nb1f4/hclkdn c17 io44pb1f4/hclkdp d17 io45nb1f4 a16 io45pb1f4 b16 io47nb1f4 h17 io47pb1f4 j17 io48nb1f4 a17 io48pb1f4 b17 io49nb1f4 h18 io49pb1f4 j18 io51nb1f4 f18 io51pb1f4 g18 io52nb1f4 b18 io53nb1f4 d18 io53pb1f4 c18 io55nb1f5 h19 io55pb1f5 g19 io56nb1f5 b19 io56pb1f5 a19 io57nb1f5 e20 io57pb1f5 e19 io58nb1f5 c20 io58pb1f5 c19 io59nb1f5 b20 io59pb1f5 a20 io61nb1f5 f20 io61pb1f5 f19 io62nb1f5 a22 io62pb1f5 a21 io63nb1f5 d21 io63pb1f5 d20 io65nb1f6 g20 fg896 ax2000 function pin number
axcelerator family fpgas revision 18 3-63 io65pb1f6 h20 io66nb1f6 b23 io66pb1f6 b21 io67nb1f6 h21 io67pb1f6 g21 io68nb1f6 d22 io68pb1f6 c22 io69nb1f6 a25 io69pb1f6 a24 io70nb1f6 f22 io70pb1f6 e22 io71nb1f6 f21 io71pb1f6 e21 io73nb1f6 c24 io73pb1f6 c23 io74nb1f6 d24 io74pb1f6 d23 io75nb1f6 h23 io75pb1f6 h22 io76nb1f7 b25 io76pb1f7 b24 io78nb1f7 b26 io78pb1f7 a26 io79nb1f7 f23 io79pb1f7 e23 io80nb1f7 d25 io80pb1f7 c25 io81nb1f7 g23 io81pb1f7 g22 io82nb1f7 b27 io82pb1f7 a27 io83nb1f7 f24 io83pb1f7 e24 io84nb1f7 d26 io84pb1f7 c26 fg896 ax2000 function pin number io85nb1f7 f25 io85pb1f7 e25 bank 2 io86nb2f8 g26 io86pb2f8 g25 io87nb2f8 k23 io87pb2f8 j23 io88nb2f8 j24 io88pb2f8 h24 io89nb2f8 e29 io89pb2f8 d29 io90nb2f8 f27 io90pb2f8 e27 io91nb2f8 h26 io91pb2f8 h25 io92nb2f8 g28 io92pb2f8 f28 io93nb2f8 j26 io93pb2f8 j25 io94nb2f8 h27 io94pb2f8 g27 io95nb2f8 h29 io95pb2f8 g29 io96nb2f9 g30 io96pb2f9 f30 io97nb2f9 k25 io97pb2f9 k24 io98nb2f9 j28 io98pb2f9 h28 io99nb2f9 l23 io99pb2f9 l24 io100nb2f9 k27 io100pb2f9 j27 io101pb2f9 j30 io102nb2f9 e30 fg896 ax2000 function pin number io102pb2f9 d30 io103nb2f9 l26 io103pb2f9 k26 io104nb2f9 f29 io105nb2f9 m25 io105pb2f9 l25 io106nb2f9 k30 io106pb2f9 k29 io107nb2f10 m23 io107pb2f10 m24 io109nb2f10 m27 io109pb2f10 l27 io110nb2f10 m28 io110pb2f10 l28 io111nb2f10 n22 io111pb2f10 n23 io112nb2f10 m29 io112pb2f10 l29 io113nb2f10 n26 io113pb2f10 m26 io114nb2f10 m30 io114pb2f10 l30 io115nb2f10 n28 io115pb2f10 n27 io117nb2f10 n25 io117pb2f10 n24 io118nb2f11 n29 io119nb2f11 p22 io119pb2f11 p23 io121nb2f11 p25 io121pb2f11 p24 io122nb2f11 p28 io122pb2f11 p27 io123nb2f11 r26 io123pb2f11 p26 fg896 ax2000 function pin number
package pin assignments 3-64 revision 18 io124nb2f11 p29 io124pb2f11 p30 io125nb2f11 r22 io125pb2f11 r23 io127nb2f11 r24 io127pb2f11 r25 io128nb2f11 r29 io128pb2f11 r30 bank 3 io129nb3f12 t27 io129pb3f12 r27 io130nb3f12 t29 io130pb3f12 t30 io131nb3f12 t22 io131pb3f12 t23 io132nb3f12 u26 io132pb3f12 t26 io133nb3f12 u24 io133pb3f12 t24 io135nb3f12 u23 io135pb3f12 u22 io136nb3f12 u29 io136pb3f12 u30 io137nb3f12 v28 io137pb3f12 u28 io138nb3f12 v27 io138pb3f12 u27 io139nb3f13 v25 io139pb3f13 u25 io141nb3f13 v23 io141pb3f13 v22 io142nb3f13 w29 io142pb3f13 v29 io143nb3f13 w26 io143pb3f13 v26 fg896 ax2000 function pin number io145nb3f13 w24 io145pb3f13 v24 io146nb3f13 w27 io146pb3f13 w28 io147nb3f13 y28 io147pb3f13 y27 io148nb3f13 y30 io148pb3f13 w30 io149nb3f13 y25 io149pb3f13 w25 io150nb3f14 aa29 io150pb3f14 y29 io151nb3f14 ac29 io152nb3f14 aa26 io152pb3f14 y26 io153nb3f14 y23 io153pb3f14 w23 io154nb3f14 ab30 io154pb3f14 aa30 io155nb3f14 ab27 io155pb3f14 aa27 io156nb3f14 ac28 io156pb3f14 ab28 io157nb3f14 aa24 io157pb3f14 y24 io158nb3f14 af29 io158pb3f14 af30 io159nb3f14 ab25 io159pb3f14 aa25 io160nb3f14 ae30 io160pb3f14 ad30 io161nb3f15 ae29 io161pb3f15 ad29 io162nb3f15 ad27 io162pb3f15 ac27 fg896 ax2000 function pin number io163nb3f15 ac26 io163pb3f15 ab26 io164nb3f15 ae28 io164pb3f15 ad28 io165nb3f15 ac24 io165pb3f15 ab24 io166nb3f15 ag28 io166pb3f15 af28 io167nb3f15 ae26 io167pb3f15 ad26 io168nb3f15 ad25 io168pb3f15 ac25 io169nb3f15 af27 io169pb3f15 ae27 io170nb3f15 ab23 io170pb3f15 aa23 bank 4 io171nb4f16 ag29 io171pb4f16 ag30 io172nb4f16 af24 io172pb4f16 af25 io173nb4f16 ag25 io173pb4f16 ag26 io174nb4f16 aj25 io174pb4f16 aj26 io175nb4f16 ak26 io175pb4f16 ak27 io176nb4f16 ae23 io176pb4f16 ae24 io177nb4f16 ah24 io177pb4f16 ah25 io178nb4f16 ad23 io178pb4f16 ac23 io179pb4f16 aj27 io180nb4f16 ag23 fg896 ax2000 function pin number
axcelerator family fpgas revision 18 3-65 io180pb4f16 ag24 io181nb4f17 ak24 io181pb4f17 ak25 io182nb4f17 ad22 io182pb4f17 ac22 io183nb4f17 af22 io183pb4f17 af23 io184nb4f17 ae21 io184pb4f17 ae22 io185nb4f17 aj23 io185pb4f17 aj24 io187nb4f17 ah22 io187pb4f17 ah23 io188nb4f17 ad21 io188pb4f17 ac21 io189pb4f17 ak22 io190nb4f17 af20 io190pb4f17 af21 io191nb4f17 ag21 io191pb4f17 ag22 io192nb4f17 ae19 io192pb4f17 ae20 io195nb4f18 ak21 io195pb4f18 aj21 io196nb4f18 ad19 io196pb4f18 ad20 io197nb4f18 aj20 io197pb4f18 ak20 io198nb4f18 ac19 io198pb4f18 ac20 io199nb4f18 ag19 io199pb4f18 ag20 io200nb4f18 ah19 io200pb4f18 ah20 io201nb4f18 ak19 fg896 ax2000 function pin number io201pb4f18 aj19 io202nb4f18 ac18 io202pb4f18 ab18 io206nb4f19 ae18 io206pb4f19 ad18 io207nb4f19 aj17 io207pb4f19 aj18 io208nb4f19 ae17 io208pb4f19 ad17 io209nb4f19 ak17 io210nb4f19 ac17 io210pb4f19 ab17 io211nb4f19 aj16 io211pb4f19 ak16 io212nb4f19/clken ag18 io212pb4f19/clkep ah18 io213nb4f19/clkfn ag16 io213pb4f19/clkfp ag17 bank 5 io214nb5f20/clkgn ag14 io214pb5f20/clkgp ag15 io215nb5f20/clkhn ag13 io215pb5f20/clkhp ah13 io216nb5f20 ab14 io216pb5f20 ac15 io217nb5f20 ak15 io217pb5f20 aj15 io218nb5f20 ae14 io218pb5f20 ad14 io219nb5f20 ak14 io219pb5f20 aj14 io222nb5f20 ab13 io222pb5f20 ac14 io223nb5f21 aj12 io223pb5f21 aj13 fg896 ax2000 function pin number io225nb5f21 ah11 io225pb5f21 ah12 io226nb5f21 ac13 io226pb5f21 ad13 io227nb5f21 ae12 io227pb5f21 ae13 io228nb5f21 ag11 io228pb5f21 ag12 io229nb5f21 ak11 io229pb5f21 ak12 io230nb5f21 ac12 io230pb5f21 ad12 io232nb5f21 ae11 io232pb5f21 af11 io233nb5f21 aj10 io233pb5f21 aj11 io234nb5f21 ac11 io234pb5f21 ad11 io236nb5f22 ak9 io236pb5f22 ak10 io237nb5f22 ag9 io237pb5f22 ag10 io238nb5f22 af9 io238pb5f22 af10 io239nb5f22 ah8 io239pb5f22 ah9 io240nb5f22 ac10 io240pb5f22 ad10 io242nb5f22 ae9 io242pb5f22 ae10 io243nb5f22 aj7 io243pb5f22 aj8 io244nb5f22 ak6 io244pb5f22 ak7 io245nb5f23 af8 fg896 ax2000 function pin number
package pin assignments 3-66 revision 18 io245pb5f23 ag8 io246nb5f23 ad8 io246pb5f23 ad9 io247nb5f23 ag7 io247pb5f23 ah7 io248nb5f23 ak5 io249nb5f23 aj5 io249pb5f23 aj6 io250nb5f23 ac8 io250pb5f23 ac9 io251nb5f23 ah6 io251pb5f23 ag6 io252nb5f23 af6 io252pb5f23 af7 io253nb5f23 ag2 io253pb5f23 ag1 io254nb5f23 ae7 io254pb5f23 ae8 io255nb5f23 ag5 io255pb5f23 ah5 io256nb5f23 aj4 io256pb5f23 ak4 bank 6 io257nb6f24 ae4 io257pb6f24 af4 io258nb6f24 ab7 io258pb6f24 ac7 io259nb6f24 ad5 io259pb6f24 ae5 io260nb6f24 af1 io260pb6f24 af2 io261nb6f24 af3 io261pb6f24 ag3 io262nb6f24 ac4 io262pb6f24 ad4 fg896 ax2000 function pin number io263nb6f24 ad3 io263pb6f24 ae3 io264nb6f24 ab6 io264pb6f24 ac6 io265nb6f24 ad1 io265pb6f24 ae1 io266nb6f24 aa8 io266pb6f24 ab8 io267nb6f25 ab5 io267pb6f25 ac5 io268nb6f25 ab3 io268pb6f25 ac3 io269nb6f25 ac2 io269pb6f25 ad2 io270nb6f25 y7 io270pb6f25 aa7 io271nb6f25 aa4 io271pb6f25 ab4 io272nb6f25 y6 io272pb6f25 aa6 io273nb6f25 ab1* io273pb6f25 ae2* io274nb6f25 w8 io274pb6f25 y8 io275nb6f25 y5 io275pb6f25 aa5 io277nb6f25 aa2 io277pb6f25 aa1 io278nb6f26 w6 io278pb6f26 w7 io279nb6f26 y3 io279pb6f26 y4 io280nb6f26 v8 io280pb6f26 v9 io281nb6f26 y1 fg896 ax2000 function pin number io281pb6f26 y2 io282nb6f26 v5 io282pb6f26 w5 io284nb6f26 v7 io284pb6f26 v6 io285nb6f26 w3 io285pb6f26 w4 io286nb6f26 u8 io286pb6f26 u9 io287nb6f26 w1 io287pb6f26 w2 io288nb6f26 u7 io288pb6f26 u6 io290nb6f27 u4 io290pb6f27 v4 io291nb6f27 u3 io291pb6f27 v3 io292nb6f27 t5 io292pb6f27 u5 io293nb6f27 u2 io293pb6f27 v2 io294nb6f27 t8 io294pb6f27 t9 io296nb6f27 t1 io296pb6f27 u1 io298nb6f27 t7 io298pb6f27 t6 io299nb6f27 r2 io299pb6f27 t2 bank 7 io300nb7f28 r8 io300pb7f28 r9 io302nb7f28 r4 io302pb7f28 r5 io303nb7f28 p1 fg896 ax2000 function pin number
axcelerator family fpgas revision 18 3-67 io303pb7f28 r1 io304nb7f28 r7 io304pb7f28 r6 io306nb7f28 n2 io306pb7f28 p2 io307nb7f28 n3 io307pb7f28 p3 io308nb7f28 p9 io308pb7f28 p8 io309nb7f28 p4 io309pb7f28 p5 io310nb7f29 p7 io310pb7f29 p6 io311nb7f29 l1 io311pb7f29 m1 io312nb7f29 m5 io312pb7f29 n5 io313nb7f29 m4 io313pb7f29 n4 io315nb7f29 l2 io315pb7f29 m2 io316nb7f29 n7 io316pb7f29 n6 io317nb7f29 l3 io317pb7f29 m3 io318nb7f29 n8 io318pb7f29 n9 io320nb7f29 l6 io320pb7f29 m6 io321nb7f30 k4 io321pb7f30 l4 io322nb7f30 m8 io322pb7f30 m7 io323nb7f30 j1 io323pb7f30 k1 fg896 ax2000 function pin number io324nb7f30 k5 io324pb7f30 l5 io326nb7f30 g1* io326pb7f30 k2* io327nb7f30 j4 io327pb7f30 j3 io328nb7f30 l8 io328pb7f30 l7 io329nb7f30 g2 io329pb7f30 h2 io330nb7f30 g3 io330pb7f30 h3 io331nb7f30 k8 io331pb7f30 k7 io332nb7f31 j6 io332pb7f31 k6 io333nb7f31 d1 io333pb7f31 d2 io334nb7f31 g4 io334pb7f31 h4 io335nb7f31 f2 io335pb7f31 f1 io336nb7f31 h5 io336pb7f31 j5 io337nb7f31 e2 io337pb7f31 e1 io338nb7f31 h7 io338pb7f31 j7 io339nb7f31 f4 io339pb7f31 f3 io340nb7f31 f5 io340pb7f31 g5 io341nb7f31 g6 io341pb7f31 h6 dedicated i/o fg896 ax2000 function pin number gnd a13 gnd a18 gnd a2 gnd a23 gnd a29 gnd a8 gnd aa10 gnd aa21 gnd aa28 gnd aa3 gnd ab2 gnd ab22 gnd ab29 gnd ab9 gnd ac1 gnd ac30 gnd ae25 gnd ae6 gnd af26 gnd af5 gnd ag27 gnd ag4 gnd ah10 gnd ah15 gnd ah16 gnd ah21 gnd ah28 gnd ah3 gnd aj1 gnd aj2 gnd aj22 gnd aj29 gnd aj30 gnd aj9 gnd ak13 fg896 ax2000 function pin number
package pin assignments 3-68 revision 18 gnd ak18 gnd ak2 gnd ak23 gnd ak29 gnd ak8 gnd b1 gnd b2 gnd b22 gnd b29 gnd b30 gnd b9 gnd c10 gnd c15 gnd c16 gnd c21 gnd c28 gnd c3 gnd d27 gnd d28 gnd d4 gnd e26 gnd e5 gnd h1 gnd h30 gnd j2 gnd j22 gnd j29 gnd j9 gnd k10 gnd k21 gnd k28 gnd k3 gnd l11 gnd l20 gnd m12 fg896 ax2000 function pin number gnd m13 gnd m14 gnd m15 gnd m16 gnd m17 gnd m18 gnd m19 gnd n1 gnd n12 gnd n13 gnd n14 gnd n15 gnd n16 gnd n17 gnd n18 gnd n19 gnd n30 gnd p12 gnd p13 gnd p14 gnd p15 gnd p16 gnd p17 gnd p18 gnd p19 gnd r12 gnd r13 gnd r14 gnd r15 gnd r16 gnd r17 gnd r18 gnd r19 gnd r28 gnd r3 fg896 ax2000 function pin number gnd t12 gnd t13 gnd t14 gnd t15 gnd t16 gnd t17 gnd t18 gnd t19 gnd t28 gnd t3 gnd u12 gnd u13 gnd u14 gnd u15 gnd u16 gnd u17 gnd u18 gnd u19 gnd v1 gnd v12 gnd v13 gnd v14 gnd v15 gnd v16 gnd v17 gnd v18 gnd v19 gnd v30 gnd w12 gnd w13 gnd w14 gnd w15 gnd w16 gnd w17 gnd w18 fg896 ax2000 function pin number
axcelerator family fpgas revision 18 3-69 gnd w19 gnd y11 gnd y20 gnd/lp e4 pra g15 prb d16 prc ab16 prd af16 tck g7 tdi d5 tdo j8 tms f6 trst c4 vcca ad6 vcca ah26 vcca e28 vcca e3 vcca l12 vcca l13 vcca l14 vcca l15 vcca l16 vcca l17 vcca l18 vcca l19 vcca m11 vcca m20 vcca n11 vcca n20 vcca p11 vcca p20 vcca r11 vcca r20 vcca t11 vcca t20 fg896 ax2000 function pin number vcca u11 vcca u20 vcca v11 vcca v20 vcca w11 vcca w20 vcca y12 vcca y13 vcca y14 vcca y15 vcca y16 vcca y17 vcca y18 vcca y19 vccda ad24 vccda ad7 vccda ae15 vccda ae16 vccda af12 vccda af13 vccda af15 vccda af18 vccda af19 vccda ah27 vccda ah4 vccda c13 vccda c27 vccda c5 vccda d13 vccda d19 vccda d3 vccda e18 vccda f15 vccda f16 vccda f26 fg896 ax2000 function pin number vccda g16 vccda t25 vccda t4 vccib0 a3 vccib0 b3 vccib0 j10 vccib0 j11 vccib0 j12 vccib0 k11 vccib0 k12 vccib0 k13 vccib0 k14 vccib0 k15 vccib1 a28 vccib1 b28 vccib1 j19 vccib1 j20 vccib1 j21 vccib1 k16 vccib1 k17 vccib1 k18 vccib1 k19 vccib1 k20 vccib2 c29 vccib2 c30 vccib2 k22 vccib2 l21 vccib2 l22 vccib2 m21 vccib2 m22 vccib2 n21 vccib2 p21 vccib2 r21 vccib3 aa22 vccib3 ah29 fg896 ax2000 function pin number note: *not routed on the same package layer and to adjacent lga pads as its differential pair complement. recommended to be used as a single-ended i/o.
package pin assignments 3-70 revision 18 vccib3 ah30 vccib3 t21 vccib3 u21 vccib3 v21 vccib3 w21 vccib3 w22 vccib3 y21 vccib3 y22 vccib4 aa16 vccib4 aa17 vccib4 aa18 vccib4 aa19 vccib4 aa20 vccib4 ab19 vccib4 ab20 vccib4 ab21 vccib4 aj28 vccib4 ak28 vccib5 aa11 vccib5 aa12 vccib5 aa13 vccib5 aa14 vccib5 aa15 vccib5 ab10 vccib5 ab11 vccib5 ab12 vccib5 aj3 vccib5 ak3 vccib6 aa9 vccib6 ah1 vccib6 ah2 vccib6 t10 vccib6 u10 vccib6 v10 vccib6 w10 fg896 ax2000 function pin number vccib6 w9 vccib6 y10 vccib6 y9 vccib7 c1 vccib7 c2 vccib7 k9 vccib7 l10 vccib7 l9 vccib7 m10 vccib7 m9 vccib7 n10 vccib7 p10 vccib7 r10 vccpla g14 vccplb h15 vccplc g17 vccpld j16 vccple ah17 vccplf ac16 vccplg ah14 vccplh ad15 vcompla f14 vcomplb j15 vcomplc f17 vcompld h16 vcomple af17 vcomplf ad16 vcomplg af14 vcomplh ab15 vpump g24 fg896 ax2000 function pin number
axcelerator family fpgas revision 18 3-71 fg1152 note for package manufacturing and environmental information, visit resource center at http://www.microsemi.com/soc/pr oducts/rescenter/package/index.html . a1 ball pad corner a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 ag ah aj ap ak al am an 31 32 33 34
package pin assignments 3-72 revision 18 fg1152 ax2000 function pin number bank 0 io00nb0f0 d6 io00pb0f0 c6 io01nb0f0 h10 io01pb0f0 h9 io02nb0f0 f8 io02pb0f0 g8 io03nb0f0 a6 io03pb0f0 b6 io04nb0f0 c7 io04pb0f0 d7 io05nb0f0 k10 io05pb0f0 j10 io06nb0f0 f9 io06pb0f0 g9 io07nb0f0 f10 io07pb0f0 g10 io08nb0f0 e9 io08pb0f0 e8 io09nb0f0 j11 io09pb0f0 k11 io10nb0f0 c8 io10pb0f0 d8 io11nb0f0 k12 io11pb0f0 j12 io12nb0f1 g11 io12pb0f1 h11 io13nb0f1 g12 io13pb0f1 h12 io14nb0f1 a7 io14pb0f1 b7 io15nb0f1 h13 io15pb0f1 j13 io16nb0f1 c9 io16pb0f1 d9 io17nb0f1 f12 io17pb0f1 f11 io18nb0f1 e11 io18pb0f1 e10 io19nb0f1 f13 io19pb0f1 g13 io20nb0f1 a10 io20pb0f1 a9 io21nb0f1 k14 io21pb0f1 k13 io22nb0f2 b11 io22pb0f2 b10 io23nb0f2 c12 io23pb0f2 c11 io24nb0f2 a12 io24pb0f2 a11 io25nb0f2 h14 io25pb0f2 j14 io26nb0f2 d13 io26pb0f2 d12 io27nb0f2 f14 io27pb0f2 g14 io28nb0f2 e14 io28pb0f2 e13 io29nb0f2 b13 io29pb0f2 b12 io30nb0f2 c14 io30pb0f2 c13 io31nb0f2 h15 io31pb0f2 j15 io32nb0f2 a14 io32pb0f2 b14 io33nb0f2 k15 io33pb0f2 l15 io34nb0f3 d15 fg1152 ax2000 function pin number io34pb0f3 d14 io35nb0f3 a15 io35pb0f3 b15 io36nb0f3 b16 io36pb0f3 a16 io37nb0f3 g16 io37pb0f3 g15 io38nb0f3 d16 io38pb0f3 c16 io39nb0f3 k16 io39pb0f3 l16 io40nb0f3 d17 io40pb0f3 c17 io41nb0f3/hclkan e16 io41pb0f3/hclkap f16 io42nb0f3/hclkbn g17 io42pb0f3/hclkbp f17 bank 1 io43nb1f4/hclkcn g19 io43pb1f4/hclkcp g18 io44nb1f4/hclkdn e19 io44pb1f4/hclkdp f19 io45nb1f4 c18 io45pb1f4 d18 io46nb1f4 a18 io46pb1f4 b18 io47nb1f4 k19 io47pb1f4 l19 io48nb1f4 c19 io48pb1f4 d19 io49nb1f4 k20 io49pb1f4 l20 io50nb1f4 a19 io50pb1f4 b19 io51nb1f4 h20 fg1152 ax2000 function pin number
axcelerator family fpgas revision 18 3-73 io51pb1f4 j20 io52nb1f4 b20 io52pb1f4 a20 io53nb1f4 f20 io53pb1f4 e20 io54nb1f5 b21 io54pb1f5 a21 io55nb1f5 k21 io55pb1f5 j21 io56nb1f5 d21 io56pb1f5 c21 io57nb1f5 g22 io57pb1f5 g21 io58nb1f5 e22 io58pb1f5 e21 io59nb1f5 d22 io59pb1f5 c22 io60nb1f5 b23 io60pb1f5 a23 io61nb1f5 h22 io61pb1f5 h21 io62nb1f5 c24 io62pb1f5 c23 io63nb1f5 f23 io63pb1f5 f22 io64nb1f6 b24 io64pb1f6 a24 io65nb1f6 j22 io65pb1f6 k22 io66nb1f6 b25 io66pb1f6 a25 io67nb1f6 k23 io67pb1f6 j23 io68nb1f6 f24 io68pb1f6 e24 fg1152 ax2000 function pin number io69nb1f6 c27 io69pb1f6 c26 io70nb1f6 h24 io70pb1f6 g24 io71nb1f6 h23 io71pb1f6 g23 io72nb1f6 b28 io72pb1f6 a28 io73nb1f6 e26 io73pb1f6 e25 io74nb1f6 f26 io74pb1f6 f25 io75nb1f6 k25 io75pb1f6 k24 io76nb1f7 d27 io76pb1f7 d26 io77nb1f7 b29 io77pb1f7 a29 io78nb1f7 d28 io78pb1f7 c28 io79nb1f7 h25 io79pb1f7 g25 io80nb1f7 f27 io80pb1f7 e27 io81nb1f7 j25 io81pb1f7 j24 io82nb1f7 d29 io82pb1f7 c29 io83nb1f7 h26 io83pb1f7 g26 io84nb1f7 f28 io84pb1f7 e28 io85nb1f7 h27 io85pb1f7 g27 bank 2 fg1152 ax2000 function pin number io86nb2f8 j28 io86pb2f8 j27 io87nb2f8 m25 io87pb2f8 l25 io88nb2f8 l26 io88pb2f8 k26 io89nb2f8 g31 io89pb2f8 f31 io90nb2f8 h29 io90pb2f8 g29 io91nb2f8 k28 io91pb2f8 k27 io92nb2f8 j30 io92pb2f8 h30 io93nb2f8 l28 io93pb2f8 l27 io94nb2f8 k29 io94pb2f8 j29 io95nb2f8 k31 io95pb2f8 j31 io96nb2f9 j32 io96pb2f9 h32 io97nb2f9 m27 io97pb2f9 m26 io98nb2f9 l30 io98pb2f9 k30 io99nb2f9 n25 io99pb2f9 n26 io100nb2f9 m29 io100pb2f9 l29 io101nb2f9 l33 io101pb2f9 l32 io102nb2f9 k34 io102pb2f9 k33 io103nb2f9 n28 fg1152 ax2000 function pin number
package pin assignments 3-74 revision 18 io103pb2f9 m28 io104nb2f9 m34 io104pb2f9 l34 io105nb2f9 p27 io105pb2f9 n27 io106nb2f9 m32 io106pb2f9 m31 io107nb2f10 p25 io107pb2f10 p26 io108nb2f10 n33 io108pb2f10 m33 io109nb2f10 p29 io109pb2f10 n29 io110nb2f10 p30 io110pb2f10 n30 io111nb2f10 r24 io111pb2f10 r25 io112nb2f10 p31 io112pb2f10 n31 io113nb2f10 r28 io113pb2f10 p28 io114nb2f10 p32 io114pb2f10 n32 io115nb2f10 r30 io115pb2f10 r29 io116nb2f10 p34 io116pb2f10 p33 io117nb2f10 r27 io117pb2f10 r26 io118nb2f11 r34 io118pb2f11 r33 io119nb2f11 t24 io119pb2f11 t25 io120nb2f11 t33 io120pb2f11 t34 fg1152 ax2000 function pin number io121nb2f11 t27 io121pb2f11 t26 io122nb2f11 t30 io122pb2f11 t29 io123nb2f11 u28 io123pb2f11 t28 io124nb2f11 t31 io124pb2f11 t32 io125nb2f11 u24 io125pb2f11 u25 io126nb2f11 u33 io126pb2f11 u34 io127nb2f11 u26 io127pb2f11 u27 io128nb2f11 u31 io128pb2f11 u32 bank 3 io129nb3f12 v29 io129pb3f12 u29 io130nb3f12 v31 io130pb3f12 v32 io131nb3f12 v24 io131pb3f12 v25 io132nb3f12 w28 io132pb3f12 v28 io133nb3f12 w26 io133pb3f12 v26 io134nb3f12 w33 io134pb3f12 v33 io135nb3f12 w25 io135pb3f12 w24 io136nb3f12 w31 io136pb3f12 w32 io137nb3f12 y30 io137pb3f12 w30 fg1152 ax2000 function pin number io138nb3f12 y29 io138pb3f12 w29 io139nb3f13 y27 io139pb3f13 w27 io140nb3f13 aa33 io140pb3f13 y33 io141nb3f13 y25 io141pb3f13 y24 io142nb3f13 aa31 io142pb3f13 y31 io143nb3f13 aa28 io143pb3f13 y28 io144nb3f13 aa34 io144pb3f13 y34 io145nb3f13 aa26 io145pb3f13 y26 io146nb3f13 aa29 io146pb3f13 aa30 io147nb3f13 ab30 io147pb3f13 ab29 io148nb3f13 ab32 io148pb3f13 aa32 io149nb3f13 ab27 io149pb3f13 aa27 io150nb3f14 ac31 io150pb3f14 ab31 io151nb3f14 ad33 io151pb3f14 ac33 io152nb3f14 ac28 io152pb3f14 ab28 io153nb3f14 ab25 io153pb3f14 aa25 io154nb3f14 ad32 io154pb3f14 ac32 io155nb3f14 ad29 fg1152 ax2000 function pin number
axcelerator family fpgas revision 18 3-75 io155pb3f14 ac29 io156nb3f14 ae30 io156pb3f14 ad30 io157nb3f14 ac26 io157pb3f14 ab26 io158nb3f14 ah33 io158pb3f14 ag33 io159nb3f14 ad27 io159pb3f14 ac27 io160nb3f14 ag32 io160pb3f14 af32 io161nb3f15 ag31 io161pb3f15 af31 io162nb3f15 af29 io162pb3f15 ae29 io163nb3f15 ae28 io163pb3f15 ad28 io164nb3f15 ag30 io164pb3f15 af30 io165nb3f15 ae26 io165pb3f15 ad26 io166nb3f15 aj30 io166pb3f15 ah30 io167nb3f15 ag28 io167pb3f15 af28 io168nb3f15 af27 io168pb3f15 ae27 io169nb3f15 ah29 io169pb3f15 ag29 io170nb3f15 ad25 io170pb3f15 ac25 bank 4 io171nb4f16 ap29 io171pb4f16 an29 io172nb4f16 ah26 fg1152 ax2000 function pin number io172pb4f16 ah27 io173nb4f16 aj27 io173pb4f16 aj28 io174nb4f16 al27 io174pb4f16 al28 io175nb4f16 am28 io175pb4f16 am29 io176nb4f16 ag25 io176pb4f16 ag26 io177nb4f16 ak26 io177pb4f16 ak27 io178nb4f16 af25 io178pb4f16 ae25 io179nb4f16 ap28 io179pb4f16 an28 io180nb4f16 aj25 io180pb4f16 aj26 io181nb4f17 am26 io181pb4f17 am27 io182nb4f17 af24 io182pb4f17 ae24 io183nb4f17 ah24 io183pb4f17 ah25 io184nb4f17 ag23 io184pb4f17 ag24 io185nb4f17 al25 io185pb4f17 al26 io186nb4f17 ap25 io186pb4f17 ap26 io187nb4f17 ak24 io187pb4f17 ak25 io188nb4f17 af23 io188pb4f17 ae23 io189nb4f17 an24 io189pb4f17 am24 fg1152 ax2000 function pin number io190nb4f17 ah22 io190pb4f17 ah23 io191nb4f17 aj23 io191pb4f17 aj24 io192nb4f17 ag21 io192pb4f17 ag22 io193nb4f18 ap23 io193pb4f18 ap24 io194nb4f18 an22 io194pb4f18 an23 io195nb4f18 am23 io195pb4f18 al23 io196nb4f18 af21 io196pb4f18 af22 io197nb4f18 al22 io197pb4f18 am22 io198nb4f18 ae21 io198pb4f18 ae22 io199nb4f18 aj21 io199pb4f18 aj22 io200nb4f18 ak21 io200pb4f18 ak22 io201nb4f18 am21 io201pb4f18 al21 io202nb4f18 ae20 io202pb4f18 ad20 io203nb4f19 an21 io203pb4f19 ap21 io204nb4f19 ap20 io204pb4f19 an20 io205nb4f19 an19 io205pb4f19 ap19 io206nb4f19 ag20 io206pb4f19 af20 io207nb4f19 al19 fg1152 ax2000 function pin number
package pin assignments 3-76 revision 18 io207pb4f19 al20 io208nb4f19 ag19 io208pb4f19 af19 io209nb4f19 an18 io209pb4f19 ap18 io210nb4f19 ae19 io210pb4f19 ad19 io211nb4f19 al18 io211pb4f19 am18 io212nb4f19/clken aj20 io212pb4f19/clkep ak20 io213nb4f19/clkfn aj18 io213pb4f19/clkfp aj19 bank 5 io214nb5f20/clkgn aj16 io214pb5f20/clkgp aj17 io215nb5f20/clkhn aj15 io215pb5f20/clkhp ak15 io216nb5f20 ad16 io216pb5f20 ae17 io217nb5f20 am17 io217pb5f20 al17 io218nb5f20 ag16 io218pb5f20 af16 io219nb5f20 am16 io219pb5f20 al16 io220nb5f20 ap16 io220pb5f20 an16 io221nb5f20 an15 io221pb5f20 ap15 io222nb5f20 ad15 io222pb5f20 ae16 io223nb5f21 al14 io223pb5f21 al15 io224nb5f21 an14 fg1152 ax2000 function pin number io224pb5f21 ap14 io225nb5f21 ak13 io225pb5f21 ak14 io226nb5f21 ae15 io226pb5f21 af15 io227nb5f21 ag14 io227pb5f21 ag15 io228nb5f21 aj13 io228pb5f21 aj14 io229nb5f21 am13 io229pb5f21 am14 io230nb5f21 ae14 io230pb5f21 af14 io231nb5f21 an12 io231pb5f21 ap12 io232nb5f21 ag13 io232pb5f21 ah13 io233nb5f21 al12 io233pb5f21 al13 io234nb5f21 ae13 io234pb5f21 af13 io235nb5f22 an11 io235pb5f22 ap11 io236nb5f22 am11 io236pb5f22 am12 io237nb5f22 aj11 io237pb5f22 aj12 io238nb5f22 ah11 io238pb5f22 ah12 io239nb5f22 ak10 io239pb5f22 ak11 io240nb5f22 ae12 io240pb5f22 af12 io241nb5f22 an10 io241pb5f22 ap10 fg1152 ax2000 function pin number io242nb5f22 ag11 io242pb5f22 ag12 io243nb5f22 al9 io243pb5f22 al10 io244nb5f22 am8 io244pb5f22 am9 io245nb5f23 ah10 io245pb5f23 aj10 io246nb5f23 af10 io246pb5f23 af11 io247nb5f23 aj9 io247pb5f23 ak9 io248nb5f23 an7 io248pb5f23 ap7 io249nb5f23 al7 io249pb5f23 al8 io250nb5f23 ae10 io250pb5f23 ae11 io251nb5f23 ak8 io251pb5f23 aj8 io252nb5f23 ah8 io252pb5f23 ah9 io253nb5f23 an6 io253pb5f23 ap6 io254nb5f23 ag9 io254pb5f23 ag10 io255nb5f23 aj7 io255pb5f23 ak7 io256nb5f23 al6 io256pb5f23 am6 bank 6 io257nb6f24 ag6 io257pb6f24 ah6 io258nb6f24 ad9 io258pb6f24 ae9 fg1152 ax2000 function pin number
axcelerator family fpgas revision 18 3-77 io259nb6f24 af7 io259pb6f24 ag7 io260nb6f24 ah3 io260pb6f24 ah4 io261nb6f24 ah5 io261pb6f24 aj5 io262nb6f24 ae6 io262pb6f24 af6 io263nb6f24 af5 io263pb6f24 ag5 io264nb6f24 ad8 io264pb6f24 ae8 io265nb6f24 af3 io265pb6f24 ag3 io266nb6f24 ac10 io266pb6f24 ad10 io267nb6f25 ad7 io267pb6f25 ae7 io268nb6f25 ad5 io268pb6f25 ae5 io269nb6f25 ae4 io269pb6f25 af4 io270nb6f25 ab9 io270pb6f25 ac9 io271nb6f25 ac6 io271pb6f25 ad6 io272nb6f25 ab8 io272pb6f25 ac8 io273nb6f25 ae1 io273pb6f25 ae2 io274nb6f25 aa10 io274pb6f25 ab10 io275nb6f25 ab7 io275pb6f25 ac7 io276nb6f25 ad1 fg1152 ax2000 function pin number io276pb6f25 ad2 io277nb6f25 ac4 io277pb6f25 ac3 io278nb6f26 aa8 io278pb6f26 aa9 io279nb6f26 ab5 io279pb6f26 ab6 io280nb6f26 y10 io280pb6f26 y11 io281nb6f26 ab3 io281pb6f26 ab4 io282nb6f26 y7 io282pb6f26 aa7 io283nb6f26 ac2 io283pb6f26 ac1 io284nb6f26 y9 io284pb6f26 y8 io285nb6f26 aa5 io285pb6f26 aa6 io286nb6f26 w10 io286pb6f26 w11 io287nb6f26 aa3 io287pb6f26 aa4 io288nb6f26 w9 io288pb6f26 w8 io289nb6f27 aa1 io289pb6f27 aa2 io290nb6f27 w6 io290pb6f27 y6 io291nb6f27 w5 io291pb6f27 y5 io292nb6f27 v7 io292pb6f27 w7 io293nb6f27 w4 io293pb6f27 y4 fg1152 ax2000 function pin number io294nb6f27 v10 io294pb6f27 v11 io295nb6f27 y1 io295pb6f27 y2 io296nb6f27 w1 io296pb6f27 w2 io297nb6f27 v1 io297pb6f27 v2 io298nb6f27 v9 io298pb6f27 v8 io299nb6f27 u4 io299pb6f27 v4 bank 7 io300nb7f28 u10 io300pb7f28 u11 io301nb7f28 u2 io301pb7f28 u1 io302nb7f28 u6 io302pb7f28 u7 io303nb7f28 t3 io303pb7f28 u3 io304nb7f28 u9 io304pb7f28 u8 io305nb7f28 r2 io305pb7f28 r1 io306nb7f28 r4 io306pb7f28 t4 io307nb7f28 r5 io307pb7f28 t5 io308nb7f28 t11 io308pb7f28 t10 io309nb7f28 t6 io309pb7f28 t7 io310nb7f29 t9 io310pb7f29 t8 fg1152 ax2000 function pin number
package pin assignments 3-78 revision 18 io311nb7f29 n3 io311pb7f29 p3 io312nb7f29 p7 io312pb7f29 r7 io313nb7f29 p6 io313pb7f29 r6 io314nb7f29 m2 io314pb7f29 n2 io315nb7f29 n4 io315pb7f29 p4 io316nb7f29 r9 io316pb7f29 r8 io317nb7f29 n5 io317pb7f29 p5 io318nb7f29 r10 io318pb7f29 r11 io319nb7f29 l2 io319pb7f29 l1 io320nb7f29 n8 io320pb7f29 p8 io321nb7f30 m6 io321pb7f30 n6 io322nb7f30 p10 io322pb7f30 p9 io323nb7f30 l3 io323pb7f30 m3 io324nb7f30 m7 io324pb7f30 n7 io325nb7f30 k2 io325pb7f30 k1 io326nb7f30 g2 io326pb7f30 h2 io327nb7f30 l6 io327pb7f30 l5 io328nb7f30 n10 fg1152 ax2000 function pin number io328pb7f30 n9 io329nb7f30 j4 io329pb7f30 k4 io330nb7f30 j5 io330pb7f30 k5 io331nb7f30 m10 io331pb7f30 m9 io332nb7f31 l8 io332pb7f31 m8 io333nb7f31 f2 io333pb7f31 f1 io334nb7f31 j6 io334pb7f31 k6 io335nb7f31 h4 io335pb7f31 h3 io336nb7f31 k7 io336pb7f31 l7 io337nb7f31 g4 io337pb7f31 g3 io338nb7f31 k9 io338pb7f31 l9 io339nb7f31 h6 io339pb7f31 h5 io340nb7f31 h7 io340pb7f31 j7 io341nb7f31 j8 io341pb7f31 k8 dedicated i/o gnd a13 gnd a2 gnd a22 gnd a27 gnd a3 gnd a31 gnd a32 fg1152 ax2000 function pin number gnd a33 gnd a4 gnd a8 gnd aa14 gnd aa15 gnd aa16 gnd aa17 gnd aa18 gnd aa19 gnd aa20 gnd aa21 gnd ab1 gnd ab13 gnd ab22 gnd ab34 gnd ac12 gnd ac23 gnd ac30 gnd ac5 gnd ad11 gnd ad24 gnd ad31 gnd ad4 gnd ae3 gnd ae32 gnd af2 gnd af33 gnd ag1 gnd ag27 gnd ag34 gnd ag8 gnd ah28 gnd ah7 gnd aj29 gnd aj6 fg1152 ax2000 function pin number
axcelerator family fpgas revision 18 3-79 gnd ak12 gnd ak17 gnd ak18 gnd ak23 gnd ak30 gnd ak5 gnd al1 gnd al11 gnd al2 gnd al24 gnd al3 gnd al31 gnd al32 gnd al33 gnd al34 gnd al4 gnd am1 gnd am10 gnd am15 gnd am2 gnd am20 gnd am25 gnd am3 gnd am31 gnd am32 gnd am33 gnd am34 gnd am4 gnd an1 gnd an2 gnd an26 gnd an3 gnd an31 gnd an32 gnd an33 fg1152 ax2000 function pin number gnd an34 gnd an4 gnd an9 gnd ap13 gnd ap2 gnd ap22 gnd ap27 gnd ap3 gnd ap31 gnd ap32 gnd ap33 gnd ap4 gnd ap8 gnd b1 gnd b2 gnd b26 gnd b3 gnd b31 gnd b32 gnd b33 gnd b34 gnd b4 gnd b9 gnd c1 gnd c10 gnd c15 gnd c2 gnd c20 gnd c25 gnd c3 gnd c31 gnd c32 gnd c33 gnd c34 gnd c4 fg1152 ax2000 function pin number gnd d1 gnd d11 gnd d2 gnd d24 gnd d3 gnd d31 gnd d32 gnd d33 gnd d34 gnd d4 gnd e12 gnd e17 gnd e18 gnd e23 gnd e30 gnd e5 gnd f29 gnd f30 gnd f6 gnd g28 gnd g7 gnd h1 gnd h34 gnd j2 gnd j33 gnd k3 gnd k32 gnd l11 gnd l24 gnd l31 gnd l4 gnd m12 gnd m23 gnd m30 gnd m5 fg1152 ax2000 function pin number
package pin assignments 3-80 revision 18 gnd n1 gnd n13 gnd n22 gnd n34 gnd p14 gnd p15 gnd p16 gnd p17 gnd p18 gnd p19 gnd p20 gnd p21 gnd r14 gnd r15 gnd r16 gnd r17 gnd r18 gnd r19 gnd r20 gnd r21 gnd r3 gnd r32 gnd t14 gnd t15 gnd t16 gnd t17 gnd t18 gnd t19 gnd t20 gnd t21 gnd u14 gnd u15 gnd u16 gnd u17 gnd u18 fg1152 ax2000 function pin number gnd u19 gnd u20 gnd u21 gnd u30 gnd u5 gnd v14 gnd v15 gnd v16 gnd v17 gnd v18 gnd v19 gnd v20 gnd v21 gnd v30 gnd v5 gnd w14 gnd w15 gnd w16 gnd w17 gnd w18 gnd w19 gnd w20 gnd w21 gnd y14 gnd y15 gnd y16 gnd y17 gnd y18 gnd y19 gnd y20 gnd y21 gnd y3 gnd y32 gnd/lp g6 nc a17 fg1152 ax2000 function pin number nc a26 nc ab2 nc ab33 nc ac34 nc ad3 nc ad34 nc ae31 nc ae33 nc ae34 nc af1 nc af34 nc ag2 nc ag4 nc ah1 nc ah2 nc ah31 nc ah32 nc ah34 nc aj1 nc aj2 nc aj3 nc aj31 nc aj32 nc aj33 nc aj34 nc aj4 nc al29 nc am19 nc am7 nc an13 nc an17 nc an25 nc an27 nc an8 nc ap17 fg1152 ax2000 function pin number
axcelerator family fpgas revision 18 3-81 nc ap9 nc b17 nc b22 nc b27 nc b8 nc d10 nc d20 nc d23 nc d25 nc f3 nc f32 nc f33 nc f34 nc f4 nc g1 nc g32 nc g33 nc g34 nc h31 nc h33 nc j1 nc j3 nc j34 nc m1 nc m4 nc p1 nc p2 nc r31 nc t1 nc t2 nc v3 nc v34 nc w3 nc w34 pra j17 fg1152 ax2000 function pin number prb f18 prc ad18 prd ah18 tck j9 tdi f7 tdo l10 tms h8 trst e6 vcca aa13 vcca aa22 vcca ab14 vcca ab15 vcca ab16 vcca ab17 vcca ab18 vcca ab19 vcca ab20 vcca ab21 vcca af8 vcca ak28 vcca g30 vcca g5 vcca n14 vcca n15 vcca n16 vcca n17 vcca n18 vcca n19 vcca n20 vcca n21 vcca p13 vcca p22 vcca r13 vcca r22 vcca t13 fg1152 ax2000 function pin number vcca t22 vcca u13 vcca u22 vcca v13 vcca v22 vcca w13 vcca w22 vcca y13 vcca y22 vccda af26 vccda af9 vccda ag17 vccda ag18 vccda ah14 vccda ah15 vccda ah17 vccda ah20 vccda ah21 vccda ak29 vccda ak6 vccda e15 vccda e29 vccda e7 vccda f15 vccda f21 vccda f5 vccda g20 vccda h17 vccda h18 vccda h28 vccda j18 vccda v27 vccda v6 vccib0 a5 vccib0 b5 fg1152 ax2000 function pin number
package pin assignments 3-82 revision 18 vccib0 c5 vccib0 d5 vccib0 l12 vccib0 l13 vccib0 l14 vccib0 m13 vccib0 m14 vccib0 m15 vccib0 m16 vccib0 m17 vccib1 a30 vccib1 b30 vccib1 c30 vccib1 d30 vccib1 l21 vccib1 l22 vccib1 l23 vccib1 m18 vccib1 m19 vccib1 m20 vccib1 m21 vccib1 m22 vccib2 e31 vccib2 e32 vccib2 e33 vccib2 e34 vccib2 m24 vccib2 n23 vccib2 n24 vccib2 p23 vccib2 p24 vccib2 r23 vccib2 t23 vccib2 u23 vccib3 aa23 fg1152 ax2000 function pin number vccib3 aa24 vccib3 ab23 vccib3 ab24 vccib3 ac24 vccib3 ak31 vccib3 ak32 vccib3 ak33 vccib3 ak34 vccib3 v23 vccib3 w23 vccib3 y23 vccib4 ac18 vccib4 ac19 vccib4 ac20 vccib4 ac21 vccib4 ac22 vccib4 ad21 vccib4 ad22 vccib4 ad23 vccib4 al30 vccib4 am30 vccib4 an30 vccib4 ap30 vccib5 ac13 vccib5 ac14 vccib5 ac15 vccib5 ac16 vccib5 ac17 vccib5 ad12 vccib5 ad13 vccib5 ad14 vccib5 al5 vccib5 am5 vccib5 an5 vccib5 ap5 fg1152 ax2000 function pin number vccib6 aa11 vccib6 aa12 vccib6 ab11 vccib6 ab12 vccib6 ac11 vccib6 ak1 vccib6 ak2 vccib6 ak3 vccib6 ak4 vccib6 v12 vccib6 w12 vccib6 y12 vccib7 e1 vccib7 e2 vccib7 e3 vccib7 e4 vccib7 m11 vccib7 n11 vccib7 n12 vccib7 p11 vccib7 p12 vccib7 r12 vccib7 t12 vccib7 u12 vccpla j16 vccplb k17 vccplc j19 vccpld l18 vccple ak19 vccplf ae18 vccplg ak16 vccplh af17 vcompla h16 vcomplb l17 vcomplc h19 fg1152 ax2000 function pin number
axcelerator family fpgas revision 18 3-83 vcompld k18 vcomple ah19 vcomplf af18 vcomplg ah16 vcomplh ad17 vpump j26 fg1152 ax2000 function pin number
package pin assignments 3-84 revision 18 pq208 note for package manufacturing and environmental information, visit resource center at http://www.microsemi.com/soc/pr oducts/rescenter/package/index.html . 208-pin pqfp 1 208
axcelerator family fpgas revision 18 3-85 pq208 ax250 function pin number bank 0 io02nb0f0 197 io03nb0f0 198 io03pb0f0 199 io12nb0f0/hclkan 191 io12pb0f0/hclkap 192 io13nb0f0/hclkbn 185 io13pb0f0/hclkbp 186 bank 1 io14nb1f1/hclkcn 180 io14pb1f1/hclkcp 181 io15nb1f1/hclkdn 174 io15pb1f1/hclkdp 175 io16nb1f1 170 io16pb1f1 171 io24nb1f1 165 io24pb1f1 166 io26nb1f1 161 io26pb1f1 162 io27nb1f1 159 io27pb1f1 160 bank 2 io29nb2f2 151 io29pb2f2 153 io30nb2f2 152 io30pb2f2 154 io31pb2f2 148 io32nb2f2 146 io32pb2f2 147 io34nb2f2 144 io34pb2f2 145 io39nb2f2 139 io39pb2f2 140 io40pb2f2 141 io41nb2f2 137 io41pb2f2 138 io43nb2f2 132 io43pb2f2 134 io44nb2f2 131 io44pb2f2 133 bank 3 io45nb3f3 127 io45pb3f3 129 io46nb3f3 126 io46pb3f3 128 io48nb3f3 122 io48pb3f3 123 io50nb3f3 120 io50pb3f3 121 io55nb3f3 116 io55pb3f3 117 io57nb3f3 114 io57pb3f3 115 io59nb3f3 110 io59pb3f3 111 io60nb3f3 108 io60pb3f3 109 io61nb3f3 106 io61pb3f3 107 bank 4 io62nb4f4 100 io62pb4f4 103 io63nb4f4 101 io63pb4f4 102 io64nb4f4 96 io64pb4f4 97 io72nb4f4 91 io72pb4f4 92 io74nb4f4/clken 87 io74pb4f4/clkep 88 io75nb4f4/clkfn 81 io75pb4f4/clkfp 82 bank 5 io76nb5f5/clkgn 76 pq208 ax250 function pin number io76pb5f5/clkgp 77 io77nb5f5/clkhn 70 io77pb5f5/clkhp 71 io78nb5f5 66 io78pb5f5 67 io86nb5f5 62 io87nb5f5 60 io87pb5f5 61 io88nb5f5 56 io88pb5f5 57 io89nb5f5 54 io89pb5f5 55 bank 6 io91nb6f6 47 io91pb6f6 49 io92nb6f6 48 io92pb6f6 50 io93nb6f6 42 io93pb6f6 43 io94pb6f6 44 io96nb6f6 40 io96pb6f6 41 io101nb6f6 35 io101pb6f6 36 io102pb6f6 37 io103nb6f6 33 io103pb6f6 34 io105nb6f6 28 io105pb6f6 30 io106nb6f6 27 io106pb6f6 29 bank 7 io107nb7f7 23 io107pb7f7 25 io108nb7f7 22 io108pb7f7 24 io110nb7f7 18 pq208 ax250 function pin number
package pin assignments 3-86 revision 18 io110pb7f7 19 io112nb7f7 16 io112pb7f7 17 io117nb7f7 12 io117pb7f7 13 io119nb7f7 10 io119pb7f7 11 io121pb7f7 7 io122nb7f7 5 io122pb7f7 6 io123nb7f7 3 io123pb7f7 4 dedicated i/o vccda 1 vccda 26 vccda 53 vccda 63 vccda 78 vccda 95 vccda 105 vccda 130 vccda 157 vccda 167 vccda 182 vccda 202 gnd 104 gnd 9 gnd 15 gnd 21 gnd 32 gnd 39 gnd 46 gnd 51 gnd 59 gnd 65 gnd 69 gnd 90 pq208 ax250 function pin number gnd 94 gnd 99 gnd 113 gnd 119 gnd 125 gnd 136 gnd 143 gnd 150 gnd 155 gnd 164 gnd 169 gnd 173 gnd 194 gnd 196 gnd 201 gnd/lp 208 pra 184 prb 183 prc 80 prd 79 tck 205 tdi 204 tdo 203 tms 206 trst 207 vcca 2 vcca 52 vcca 156 vcca 14 vcca 38 vcca 64 vcca 93 vcca 118 vcca 142 vcca 168 vcca 195 vccpla 189 pq208 ax250 function pin number vccplb 187 vccplc 178 vccpld 176 vccple 85 vccplf 83 vccplg 74 vccplh 72 vccib0 193 vccib0 200 vccib1 163 vccib1 172 vccib2 135 vccib2 149 vccib3 112 vccib3 124 vccib4 89 vccib4 98 vccib5 58 vccib5 68 vccib6 31 vccib6 45 vccib7 8 vccib7 20 vcompla 190 vcomplb 188 vcomplc 179 vcompld 177 vcomple 86 vcomplf 84 vcomplg 75 vcomplh 73 vpump 158 pq208 ax250 function pin number
axcelerator family fpgas revision 18 3-87 pq208 AX500 function pin number bank 0 io03nb0f0 198 io03pb0f0 199 io04nb0f0 197 io19nb0f1/hclkan 191 io19pb0f1/hclkap 192 io20nb0f1/hclkbn 185 io20pb0f1/hclkbp 186 bank 1 io21nb1f2/hclkcn 180 io21pb1f2/hclkcp 181 io22nb1f2/hclkdn 174 io22pb1f2/hclkdp 175 io23nb1f2 170 io23pb1f2 171 io37nb1f3 165 io37pb1f3 166 io39nb1f3 161 io39pb1f3 162 io41nb1f3 159 io41pb1f3 160 bank 2 io43nb2f4 151 io43pb2f4 153 io44nb2f4 152 io44pb2f4 154 io45pb2f4 148 io46nb2f4 146 io46pb2f4 147 io48nb2f4 144 io48pb2f4 145 io57nb2f5 139 io57pb2f5 140 io58pb2f5 141 io59nb2f5 137 io59pb2f5 138 io61nb2f5 132 io61pb2f5 134 io62nb2f5 131 io62pb2f5 133 bank 3 io63nb3f6 127 io63pb3f6 129 io64nb3f6 126 io64pb3f6 128 io66nb3f6 122 io66pb3f6 123 io68nb3f6 120 io68pb3f6 121 io77nb3f7 116 io77pb3f7 117 io79nb3f7 114 io79pb3f7 115 io81nb3f7 110 io81pb3f7 111 io82nb3f7 108 io82pb3f7 109 io83nb3f7 106 io83pb3f7 107 bank 4 io84pb4f8 103 io85nb4f8 100 io86nb4f8 101 io86pb4f8 102 io87nb4f8 96 io87pb4f8 97 io101nb4f9 91 io101pb4f9 92 io103nb4f9/clken 87 io103pb4f9/clkep 88 io104nb4f9/clkfn 81 io104pb4f9/clkfp 82 bank 5 io105nb5f10/clkgn 76 pq208 AX500 function pin number io105pb5f10/clkgp 77 io106nb5f10/clkhn 70 io106pb5f10/clkhp 71 io107nb5f10 66 io107pb5f10 67 io119nb5f11 62 io121nb5f11 60 io121pb5f11 61 io123nb5f11 56 io123pb5f11 57 io125nb5f11 54 io125pb5f11 55 bank 6 io127nb6f12 47 io127pb6f12 49 io128nb6f12 48 io128pb6f12 50 io129nb6f12 42 io129pb6f12 43 io130pb6f12 44 io132nb6f12 40 io132pb6f12 41 io141nb6f13 35 io141pb6f13 36 io142pb6f13 37 io143nb6f13 33 io143pb6f13 34 io145nb6f13 28 io145pb6f13 30 io146nb6f13 27 io146pb6f13 29 bank 7 io147nb7f14 23 io147pb7f14 25 io148nb7f14 22 io148pb7f14 24 io150nb7f14 18 pq208 AX500 function pin number
package pin assignments 3-88 revision 18 io150pb7f14 19 io152nb7f14 16 io152pb7f14 17 io161nb7f15 12 io161pb7f15 13 io163nb7f15 10 io163pb7f15 11 io165pb7f15 7 io166nb7f15 5 io166pb7f15 6 io167nb7f15 3 io167pb7f15 4 dedicated i/o v ccda 1 v ccda 26 v ccda 53 v ccda 63 v ccda 78 v ccda 95 v ccda 105 v ccda 130 v ccda 157 v ccda 167 v ccda 182 v ccda 202 gnd 104 gnd 9 gnd 15 gnd 21 gnd 32 gnd 39 gnd 46 gnd 51 gnd 59 gnd 65 gnd 69 gnd 90 pq208 AX500 function pin number gnd 94 gnd 99 gnd 113 gnd 119 gnd 125 gnd 143 gnd 136 gnd 150 gnd 155 gnd 164 gnd 169 gnd 173 gnd 194 gnd 196 gnd 201 gnd/lp 208 pra 184 prb 183 prc 80 prd 79 tck 205 tdi 204 tdo 203 tms 206 trst 207 vcca 2 vcca 14 vcca 38 vcca 52 vcca 64 vcca 93 vcca 118 vcca 142 vcca 156 vcca 168 vcca 195 vccpla 189 pq208 AX500 function pin number vccplb 187 vccplc 178 vccpld 176 vccple 85 vccplf 83 vccplg 74 vccplh 72 vccib0 200 vccib0 193 vccib1 172 vccib1 163 vccib2 149 vccib2 135 vccib3 124 vccib3 112 vccib4 98 vccib4 89 vccib5 68 vccib5 58 vccib6 45 vccib6 31 vccib7 20 vccib7 8 vcompla 190 vcomplb 188 vcomplc 179 vcompld 177 vcomple 86 vcomplf 84 vcomplg 75 vcomplh 73 vpump 158 pq208 AX500 function pin number
axcelerator family fpgas revision 18 3-89 cq208 note for package manufacturing and environmental information, visit resource center at http://www.microsemi.com/soc/pr oducts/rescenter/package/index.html . ceramic tie bar 208-pin cqfp 1 2 3 4 49 50 51 52 53 54 55 56 101 102 103 104 156 155 154 153 108 107 106 105 208 207 206 205 160 159 158 157 pin 1
package pin assignments 3-90 revision 18 cq208 ax250 function pin number bank 0 io02nb0f0 197 io03nb0f0 198 io03pb0f0 199 io12nb0f0/hclkan 191 io12pb0f0/hclkap 192 io13nb0f0/hclkbn 185 io13pb0f0/hclkbp 186 bank 1 io14nb1f1/hclkcn 180 io14pb1f1/hclkcp 181 io15nb1f1/hclkdn 174 io15pb1f1/hclkdp 175 io16nb1f1 170 io16pb1f1 171 io24nb1f1 165 io24pb1f1 166 io26nb1f1 161 io26pb1f1 162 io27nb1f1 159 io27pb1f1 160 bank 2 io29nb2f2 151 io29pb2f2 153 io30nb2f2 152 io30pb2f2 154 io31pb2f2 148 io32nb2f2 146 io32pb2f2 147 io34nb2f2 144 io34pb2f2 145 io39nb2f2 139 io39pb2f2 140 io40pb2f2 141 io41nb2f2 137 io41pb2f2 138 io43nb2f2 132 io43pb2f2 134 io44nb2f2 131 io44pb2f2 133 bank 3 io45nb3f3 127 io45pb3f3 129 io46nb3f3 126 io46pb3f3 128 io48nb3f3 122 io48pb3f3 123 io50nb3f3 120 io50pb3f3 121 io55nb3f3 116 io55pb3f3 117 io57nb3f3 114 io57pb3f3 115 io59nb3f3 110 io59pb3f3 111 io60nb3f3 108 io60pb3f3 109 io61nb3f3 106 io61pb3f3 107 bank 4 io62nb4f4 100 io62pb4f4 103 io63nb4f4 101 io63pb4f4 102 io64nb4f4 96 io64pb4f4 97 io72nb4f4 91 io72pb4f4 92 io74nb4f4/clken 87 io74pb4f4/clkep 88 io75nb4f4/clkfn 81 io75pb4f4/clkfp 82 bank 5 io76nb5f5/clkgn 76 cq208 ax250 function pin number io76pb5f5/clkgp 77 io77nb5f5/clkhn 70 io77pb5f5/clkhp 71 io78nb5f5 66 io78pb5f5 67 io86nb5f5 62 io87nb5f5 60 io87pb5f5 61 io88nb5f5 56 io88pb5f5 57 io89nb5f5 54 io89pb5f5 55 bank 6 io91nb6f6 47 io91pb6f6 49 io92nb6f6 48 io92pb6f6 50 io93nb6f6 42 io93pb6f6 43 io94pb6f6 44 io96nb6f6 40 io96pb6f6 41 io101nb6f6 35 io101pb6f6 36 io102pb6f6 37 io103nb6f6 33 io103pb6f6 34 io105nb6f6 28 io105pb6f6 30 io106nb6f6 27 io106pb6f6 29 bank 7 io107nb7f7 23 io107pb7f7 25 io108nb7f7 22 io108pb7f7 24 io110nb7f7 18 cq208 ax250 function pin number
axcelerator family fpgas revision 18 3-91 io110pb7f7 19 io112nb7f7 16 io112pb7f7 17 io117nb7f7 12 io117pb7f7 13 io119nb7f7 10 io119pb7f7 11 io121pb7f7 7 io122nb7f7 5 io122pb7f7 6 io123nb7f7 3 io123pb7f7 4 dedicated i/o gnd 9 gnd 15 gnd 21 gnd 32 gnd 39 gnd 46 gnd 51 gnd 59 gnd 65 gnd 69 gnd 90 gnd 94 gnd 99 gnd 104 gnd 113 gnd 119 gnd 125 gnd 136 gnd 143 gnd 150 gnd 155 gnd 164 gnd 169 gnd 173 cq208 ax250 function pin number gnd 194 gnd 196 gnd 201 gnd/lp 208 pra 184 prb 183 prc 80 prd 79 tck 205 tdi 204 tdo 203 tms 206 trst 207 vcca 2 vcca 14 vcca 38 vcca 52 vcca 64 vcca 93 vcca 118 vcca 142 vcca 156 vcca 168 vcca 195 vccda 1 vccda 26 vccda 53 vccda 63 vccda 78 vccda 95 vccda 105 vccda 130 vccda 157 vccda 167 vccda 182 vccda 202 vccib0 193 cq208 ax250 function pin number vccib0 200 vccib1 163 vccib1 172 vccib2 135 vccib2 149 vccib3 112 vccib3 124 vccib4 89 vccib4 98 vccib5 58 vccib5 68 vccib6 31 vccib6 45 vccib7 8 vccib7 20 vccpla 189 vccplb 187 vccplc 178 vccpld 176 vccple 85 vccplf 83 vccplg 74 vccplh 72 vcompla 190 vcomplb 188 vcomplc 179 vcompld 177 vcomple 86 vcomplf 84 vcomplg 75 vcomplh 73 vpump 158 cq208 ax250 function pin number
package pin assignments 3-92 revision 18 cq208 AX500 function pin number bank 0 io03nb0f0 198 io03pb0f0 199 io04nb0f0 197 io19nb0f1/hclkan 191 io19pb0f1/hclkap 192 io20nb0f1/hclkbn 185 io20pb0f1/hclkbp 186 bank 1 io21nb1f2/hclkcn 180 io21pb1f2/hclkcp 181 io22nb1f2/hclkdn 174 io22pb1f2/hclkdp 175 io23nb1f2 170 io23pb1f2 171 io37nb1f3 165 io37pb1f3 166 io39nb1f3 161 io39pb1f3 162 io41nb1f3 159 io41pb1f3 160 bank 2 io43nb2f4 151 io43pb2f4 153 io44nb2f4 152 io44pb2f4 154 io45pb2f4 148 io46nb2f4 146 io46pb2f4 147 io48nb2f4 144 io48pb2f4 145 io57nb2f5 139 io57pb2f5 140 io58pb2f5 141 io59nb2f5 137 io59pb2f5 138 io61nb2f5 132 io61pb2f5 134 io62nb2f5 131 io62pb2f5 133 bank 3 io63nb3f6 127 io63pb3f6 129 io64nb3f6 126 io64pb3f6 128 io66nb3f6 122 io66pb3f6 123 io68nb3f6 120 io68pb3f6 121 io77nb3f7 116 io77pb3f7 117 io79nb3f7 114 io79pb3f7 115 io81nb3f7 110 io81pb3f7 111 io82nb3f7 108 io82pb3f7 109 io83nb3f7 106 io83pb3f7 107 bank 4 io84pb4f8 103 io85nb4f8 100 io86nb4f8 101 io86pb4f8 102 io87nb4f8 96 io87pb4f8 97 io101nb4f9 91 io101pb4f9 92 io103nb4f9/clken 87 io103pb4f9/clkep 88 io104nb4f9/clkfn 81 io104pb4f9/clkfp 82 bank 5 io105nb5f10/clkgn 76 cq208 AX500 function pin number io105pb5f10/clkgp 77 io106nb5f10/clkhn 70 io106pb5f10/clkhp 71 io107nb5f10 66 io107pb5f10 67 io119nb5f11 62 io121nb5f11 60 io121pb5f11 61 io123nb5f11 56 io123pb5f11 57 io125nb5f11 54 io125pb5f11 55 bank 6 io127nb6f12 47 io127pb6f12 49 io128nb6f12 48 io128pb6f12 50 io129nb6f12 42 io129pb6f12 43 io130pb6f12 44 io132nb6f12 40 io132pb6f12 41 io141nb6f13 35 io141pb6f13 36 io142pb6f13 37 io143nb6f13 33 io143pb6f13 34 io145nb6f13 28 io145pb6f13 30 io146nb6f13 27 io146pb6f13 29 bank 7 io147nb7f14 23 io147pb7f14 25 io148nb7f14 22 io148pb7f14 24 io150nb7f14 18 cq208 AX500 function pin number
axcelerator family fpgas revision 18 3-93 io150pb7f14 19 io152nb7f14 16 io152pb7f14 17 io161nb7f15 12 io161pb7f15 13 io163nb7f15 10 io163pb7f15 11 io165pb7f15 7 io166nb7f15 5 io166pb7f15 6 io167nb7f15 3 io167pb7f15 4 dedicated i/o vccda 1 gnd 9 gnd 15 gnd 21 gnd 32 gnd 39 gnd 46 gnd 51 gnd 59 gnd 65 gnd 69 gnd 90 gnd 94 gnd 99 gnd 104 gnd 113 gnd 119 gnd 125 gnd 136 gnd 143 gnd 150 gnd 155 gnd 164 gnd 169 cq208 AX500 function pin number gnd 173 gnd 194 gnd 196 gnd 201 gnd/lp 208 pra 184 prb 183 prc 80 prd 79 tck 205 tdi 204 tdo 203 tms 206 trst 207 vcca 2 vcca 14 vcca 38 vcca 52 vcca 64 vcca 93 vcca 118 vcca 142 vcca 156 vcca 168 vcca 195 vccda 26 vccda 53 vccda 63 vccda 78 vccda 95 vccda 105 vccda 130 vccda 157 vccda 167 vccda 182 vccda 202 vccib0 193 cq208 AX500 function pin number vccib0 200 vccib1 163 vccib1 172 vccib2 135 vccib2 149 vccib3 112 vccib3 124 vccib4 89 vccib4 98 vccib5 58 vccib5 68 vccib6 31 vccib6 45 vccib7 8 vccib7 20 vccpla 189 vccplb 187 vccplc 178 vccpld 176 vccple 85 vccplf 83 vccplg 74 vccplh 72 vcompla 190 vcomplb 188 vcomplc 179 vcompld 177 vcomple 86 vcomplf 84 vcomplg 75 vcomplh 73 vpump 158 cq208 AX500 function pin number
package pin assignments 3-94 revision 18 cq256 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx . ceramic tie bar 256-pin cqfp 1 2 3 4 61 62 63 64 65 66 67 68 125 126 127 128 192 191 190 189 132 131 130 129 256 255 254 253 196 195 194 193 pin 1
axcelerator family fpgas revision 18 3-95 cq256 ax2000 function pin number bank 0 io01nb0f0 248 io01pb0f0 249 io04nb0f0 246 io04pb0f0 247 io05nb0f0 242 io05pb0f0 243 io08nb0f0 240 io08pb0f0 241 bank 0 io37nb0f3 234 io37pb0f3 235 io41nb0f3/hclkan 232 io41pb0f3/hclkap 233 io42nb0f3/hclkbn 228 io42pb0f3/hclkbp 229 bank 1 - io43nb1f4/hclkcn 220 io43pb1f4/hclkcp 221 io44nb1f4/hclkdn 216 io44pb1f4/hclkdp 217 bank 1 io65nb1f6 210 io65pb1f6 211 io69nb1f6 208 io69pb1f6 209 io70nb1f6 199 io71nb1f6 204 io71pb1f6 205 io73nb1f6 202 io73pb1f6 203 io74nb1f6 197 io74pb1f6 198 bank 2 io87nb2f8 187 io87pb2f8 188 io89pb2f8 186 bank 2 io107nb2f10 184 io107pb2f10 185 io110nb2f10 180 io110pb2f10 181 io111nb2f10 178 io111pb2f10 179 io112nb2f10 174 io112pb2f10 175 io113nb2f10 172 io113pb2f10 173 io114nb2f10 168 io114pb2f10 169 io115nb2f10 166 io115pb2f10 167 io117nb2f10 162 io117pb2f10 163 bank 3 io139nb3f13 158 io139pb3f13 159 io141nb3f13 154 io141pb3f13 155 io142nb3f13 152 io142pb3f13 153 io145nb3f13 148 io145pb3f13 149 io146nb3f13 146 io146pb3f13 147 io147nb3f13 140 io147pb3f13 141 io148nb3f13 142 io148pb3f13 143 io149nb3f13 136 cq256 ax2000 function pin number io149pb3f13 137 bank 3 io165nb3f15 135 io167nb3f15 133 io167pb3f15 134 bank 4 io181nb4f17 124 io181pb4f17 125 io182nb4f17 122 io182pb4f17 123 io183nb4f17 118 io183pb4f17 119 io184nb4f17 116 io184pb4f17 117 io190nb4f17 112 io190pb4f17 113 io192nb4f17 110 io192pb4f17 111 bank 4 io212nb4f19/clken 104 io212pb4f19/clkep 105 io213nb4f19/clkfn 100 io213pb4f19/clkfp 101 bank 5 io214nb5f20/clkgn 92 io214pb5f20/clkgp 93 io215nb5f20/clkhn 88 io215pb5f20/clkhp 89 bank 5 io236nb5f22 82 io236pb5f22 83 io238nb5f22 80 io238pb5f22 81 io240nb5f22 76 io240pb5f22 77 cq256 ax2000 function pin number
package pin assignments 3-96 revision 18 io242nb5f22 74 io242pb5f22 75 io243nb5f22 70 io243pb5f22 71 io244nb5f22 68 io244pb5f22 69 bank 6 io257pb6f24 60 io258nb6f24 58 io258pb6f24 59 bank 6 io279nb6f26 56 io279pb6f26 57 io280nb6f26 52 io280pb6f26 53 io281nb6f26 50 io281pb6f26 51 io282nb6f26 46 io282pb6f26 47 io284nb6f26 44 io284pb6f26 45 io285nb6f26 40 io285pb6f26 41 io286nb6f26 38 io286pb6f26 39 io287nb6f26 34 io287pb6f26 35 bank 7 9 io310nb7f29 30 io310pb7f29 31 io311nb7f29 26 io311pb7f29 27 io312nb7f29 24 io312pb7f29 25 io315nb7f29 20 cq256 ax2000 function pin number io315pb7f29 21 io316nb7f29 18 io316pb7f29 19 io317nb7f29 14 io317pb7f29 15 io318nb7f29 12 io318pb7f29 13 io320nb7f29 8 io320pb7f29 9 bank 7 io341nb7f31 6 io341pb7f31 7 dedicated i/o gnd 1 gnd 5 gnd 11 gnd 17 gnd 23 gnd 29 gnd 33 gnd 37 gnd 43 gnd 49 gnd 55 gnd 62 gnd 64 gnd 65 gnd 73 gnd 79 gnd 85 gnd 91 gnd 97 gnd 103 gnd 109 gnd 115 cq256 ax2000 function pin number gnd 121 gnd 128 gnd 129 gnd 132 gnd 139 gnd 145 gnd 151 gnd 157 gnd 161 gnd 165 gnd 171 gnd 177 gnd 183 gnd 190 gnd 192 gnd 193 gnd 201 gnd 207 gnd 213 gnd 219 gnd 225 gnd 231 gnd 239 gnd 245 gnd 256 pra 227 prb 226 prc 99 prd 98 tck 253 tdi 252 tdo 250 tms 254 trst 255 vcca 3 cq256 ax2000 function pin number
axcelerator family fpgas revision 18 3-97 vcca 4 vcca 22 vcca 42 vcca 61 vcca 63 vcca 84 vcca 108 vcca 127 vcca 131 vcca 150 vcca 170 vcca 189 vcca 191 vcca 212 vcca 238 vccda 2 vccda 32 vccda 66 vccda 67 vccda 86 vccda 87 vccda 94 vccda 95 vccda 96 vccda 106 vccda 107 vccda 126 vccda 130 vccda 160 vccda 194 vccda 196 vccda 214 vccda 215 vccda 222 vccda 223 cq256 ax2000 function pin number vccda 224 vccda 236 vccda 237 vccda 251 vccib0 230 vccib0 244 vccib1 200 vccib1 206 vccib1 218 vccib2 164 vccib2 176 vccib2 182 vccib3 138 vccib3 144 vccib3 156 vccib4 102 vccib4 114 vccib4 120 vccib5 72 vccib5 78 vccib5 90 vccib6 36 vccib6 48 vccib6 54 vccib7 10 vccib7 16 vccib7 28 vpump 195 cq256 ax2000 function pin number
package pin assignments 3-98 revision 18 cq352 note for package manufacturing and environmental information, visit resource center at http://www.microsemi.com/soc/pr oducts/rescenter/package/index.html . ceramic tie bar pin 1 352-pin cqfp 1 2 3 4 264 263 262 261 41 42 43 44 45 46 47 48 49 85 86 87 88 180 179 178 177 223 222 221 220 219 218 217 216 215 352 351 350 349 339 338 337 336 335 334 333 332 331 268 267 266 265 89 90 91 92 127 128 129 130 131 132 133 134 135 173 174 175 176
axcelerator family fpgas revision 18 3-99 cq352 ax250 function pin number bank 0 io00nb0f0 341 io00pb0f0 342 io01nb0f0 343 io02nb0f0 337 io02pb0f0 338 io04nb0f0 335 io04pb0f0 336 io06nb0f0 331 io06pb0f0 332 io08nb0f0 325 io08pb0f0 326 io10nb0f0 323 io10pb0f0 324 io12nb0f0/hclkan 319 io12pb0f0/hclkap 320 io13nb0f0/hclkbn 313 io13pb0f0/hclkbp 314 bank 1 io14nb1f1/hclkcn 305 io14pb1f1/hclkcp 306 io15nb1f1/hclkdn 299 io15pb1f1/hclkdp 300 io16nb1f1 289 io16pb1f1 290 io17nb1f1 295 io17pb1f1 296 io18nb1f1 287 io18pb1f1 288 io20nb1f1 283 io20pb1f1 284 io22nb1f1 277 io22pb1f1 278 io23nb1f1 281 io23pb1f1 282 io24nb1f1 275 io24pb1f1 276 io25nb1f1 271 io25pb1f1 272 io27nb1f1 269 io27pb1f1 270 bank 2 io29nb2f2 261 io29pb2f2 262 io30nb2f2 259 io30pb2f2 260 io31nb2f2 255 io31pb2f2 256 io33nb2f2 249 io33pb2f2 250 io34nb2f2 253 io34pb2f2 254 io35nb2f2 247 io35pb2f2 248 io36nb2f2 243 io36pb2f2 244 io37nb2f2 241 io37pb2f2 242 io38nb2f2 237 io38pb2f2 238 io39nb2f2 235 io39pb2f2 236 io41nb2f2 231 io41pb2f2 232 io42nb2f2 229 io42pb2f2 230 io43nb2f2 225 io43pb2f2 226 io44nb2f2 223 io44pb2f2 224 cq352 ax250 function pin number bank 3 io45nb3f3 217 io45pb3f3 218 io46nb3f3 219 io46pb3f3 220 io47nb3f3 213 io47pb3f3 214 io48nb3f3 211 io48pb3f3 212 io49nb3f3 207 io49pb3f3 208 io51nb3f3 205 io51pb3f3 206 io52nb3f3 201 io52pb3f3 202 io53nb3f3 199 io53pb3f3 200 io54nb3f3 195 io54pb3f3 196 io55nb3f3 193 io55pb3f3 194 io56nb3f3 187 io56pb3f3 188 io57nb3f3 189 io57pb3f3 190 io59nb3f3 183 io59pb3f3 184 io60nb3f3 181 io60pb3f3 182 io61nb3f3 179 io61pb3f3 180 bank 4 io62nb4f4 172 io62pb4f4 173 io64nb4f4 166 cq352 ax250 function pin number
package pin assignments 3-100 revision 18 io64pb4f4 167 io65nb4f4 170 io65pb4f4 171 io66nb4f4 164 io66pb4f4 165 io67nb4f4 160 io67pb4f4 161 io68nb4f4 158 io68pb4f4 159 io70nb4f4 154 io70pb4f4 155 io72nb4f4 152 io72pb4f4 153 io73nb4f4 146 io73pb4f4 147 io74nb4f4/clken 142 io74pb4f4/clkep 143 io75nb4f4/clkfn 136 io75pb4f4/clkfp 137 bank 5 io76nb5f5/clkgn 128 io76pb5f5/clkgp 129 io77nb5f5/clkhn 122 io77pb5f5/clkhp 123 io78nb5f5 112 io78pb5f5 113 io79nb5f5 118 io79pb5f5 119 io80nb5f5 110 io80pb5f5 111 io82nb5f5 106 io82pb5f5 107 io84nb5f5 100 io84pb5f5 101 io85nb5f5 104 cq352 ax250 function pin number io85pb5f5 105 io86nb5f5 98 io86pb5f5 99 io87nb5f5 94 io87pb5f5 95 io89nb5f5 92 io89pb5f5 93 bank 6 io90pb6f6 86 io91nb6f6 84 io91pb6f6 85 io92nb6f6 78 io92pb6f6 79 io93nb6f6 82 io93pb6f6 83 io95nb6f6 76 io95pb6f6 77 io96nb6f6 72 io96pb6f6 73 io97nb6f6 70 io97pb6f6 71 io98nb6f6 66 io98pb6f6 67 io99nb6f6 64 io99pb6f6 65 io100nb6f6 60 io100pb6f6 61 io101nb6f6 58 io101pb6f6 59 io103nb6f6 54 io103pb6f6 55 io104nb6f6 52 io104pb6f6 53 io105nb6f6 48 io105pb6f6 49 cq352 ax250 function pin number io106nb6f6 46 io106pb6f6 47 bank 7 io107nb7f7 40 io107pb7f7 41 io108nb7f7 42 io108pb7f7 43 io109nb7f7 36 io109pb7f7 37 io110nb7f7 34 io110pb7f7 35 io111nb7f7 30 io111pb7f7 31 io113nb7f7 28 io113pb7f7 29 io114nb7f7 24 io114pb7f7 25 io115nb7f7 22 io115pb7f7 23 io116nb7f7 18 io116pb7f7 19 io117nb7f7 16 io117pb7f7 17 io118nb7f7 12 io118pb7f7 13 io119nb7f7 10 io119pb7f7 11 io121nb7f7 6 io121pb7f7 7 io123nb7f7 4 io123pb7f7 5 dedicated i/o gnd 1 gnd 9 gnd 15 cq352 ax250 function pin number
axcelerator family fpgas revision 18 3-101 gnd 21 gnd 27 gnd 33 gnd 39 gnd 45 gnd 51 gnd 57 gnd 63 gnd 69 gnd 75 gnd 81 gnd 88 gnd 89 gnd 97 gnd 103 gnd 109 gnd 115 gnd 121 gnd 133 gnd 145 gnd 151 gnd 157 gnd 163 gnd 169 gnd 176 gnd 177 gnd 186 gnd 192 gnd 198 gnd 204 gnd 210 gnd 216 gnd 222 gnd 228 gnd 234 cq352 ax250 function pin number gnd 240 gnd 246 gnd 252 gnd 258 gnd 264 gnd 265 gnd 274 gnd 280 gnd 286 gnd 292 gnd 298 gnd 310 gnd 322 gnd 330 gnd 334 gnd 340 gnd 345 gnd 352 nc 91 nc 117 nc 130 nc 131 nc 148 nc 174 nc 268 nc 294 nc 307 nc 308 nc 327 nc 328 pra 312 prb 311 prc 135 prd 134 tck 349 cq352 ax250 function pin number tdi 348 tdo 347 tms 350 trst 351 vcca 3 vcca 14 vcca 32 vcca 56 vcca 74 vcca 87 vcca 102 vcca 114 vcca 150 vcca 162 vcca 175 vcca 191 vcca 209 vcca 233 vcca 251 vcca 263 vcca 279 vcca 291 vcca 329 vcca 339 vccda 2 vccda 44 vccda 90 vccda 116 vccda 132 vccda 149 vccda 178 vccda 221 vccda 266 vccda 293 vccda 309 cq352 ax250 function pin number
package pin assignments 3-102 revision 18 vccda 346 vccib0 321 vccib0 333 vccib0 344 vccib1 273 vccib1 285 vccib1 297 vccib2 227 vccib2 239 vccib2 245 vccib2 257 vccib3 185 vccib3 197 vccib3 203 vccib3 215 vccib4 144 vccib4 156 vccib4 168 vccib5 96 vccib5 108 vccib5 120 vccib6 50 vccib6 62 vccib6 68 vccib6 80 vccib7 8 vccib7 20 vccib7 26 vccib7 38 vccpla 317 vccplb 315 vccplc 303 vccpld 301 vccple 140 vccplf 138 cq352 ax250 function pin number vccplg 126 vccplh 124 vcompla 318 vcomplb 316 vcomplc 304 vcompld 302 vcomple 141 vcomplf 139 vcomplg 127 vcomplh 125 vpump 267 cq352 ax250 function pin number
axcelerator family fpgas revision 18 3-103 cq352 AX500 function pin number bank 0 io00pb0f0 343 io03nb0f0 341 io03pb0f0 342 io05nb0f0 337 io05pb0f0 338 io07nb0f0 335 io07pb0f0 336 io09nb0f0 331 io09pb0f0 332 io15nb0f1 325 io15pb0f1 326 io17nb0f1 323 io17pb0f1 324 io19nb0f1/hclkan 319 io19pb0f1/hclkap 320 io20nb0f1/hclkbn 313 io20pb0f1/hclkbp 314 bank 1 io21nb1f2/hclkcn 305 io21pb1f2/hclkcp 306 io22nb1f2/hclkdn 299 io22pb1f2/hclkdp 300 io23nb1f2 289 io23pb1f2 290 io24nb1f2 295 io24pb1f2 296 io25nb1f2 287 io25pb1f2 288 io27nb1f2 283 io27pb1f2 284 io29nb1f2 281 io29pb1f2 282 io31nb1f2 277 io31pb1f2 278 io35nb1f3 275 io35pb1f3 276 io37nb1f3 271 io37pb1f3 272 io41nb1f3 269 io41pb1f3 270 bank 2 io43nb2f4 261 io43pb2f4 262 io45nb2f4 259 io45pb2f4 260 io47nb2f4 255 io47pb2f4 256 io49nb2f4 253 io49pb2f4 254 io50nb2f4 247 io50pb2f4 248 io51nb2f4 249 io51pb2f4 250 io53nb2f5 243 io53pb2f5 244 io54nb2f5 241 io54pb2f5 242 io55nb2f5 237 io55pb2f5 238 io57nb2f5 235 io57pb2f5 236 io58nb2f5 231 io58pb2f5 232 io59nb2f5 229 io59pb2f5 230 io61nb2f5 225 io61pb2f5 226 io62nb2f5 223 io62pb2f5 224 cq352 AX500 function pin number bank 3 io63nb3f6 217 io63pb3f6 218 io64nb3f6 219 io64pb3f6 220 io65nb3f6 213 io65pb3f6 214 io67nb3f6 207 io67pb3f6 208 io68nb3f6 211 io68pb3f6 212 io69nb3f6 205 io69pb3f6 206 io71nb3f6 201 io71pb3f6 202 io73nb3f6 199 io73pb3f6 200 io75nb3f7 193 io75pb3f7 194 io76nb3f7 195 io76pb3f7 196 io77nb3f7 189 io77pb3f7 190 io79nb3f7 187 io79pb3f7 188 io80nb3f7 183 io80pb3f7 184 io81nb3f7 181 io81pb3f7 182 io83nb3f7 179 io83pb3f7 180 bank 4 io85nb4f8 172 io85pb4f8 173 io87nb4f8 170 cq352 AX500 function pin number
package pin assignments 3-104 revision 18 io87pb4f8 171 io89nb4f8 166 io89pb4f8 167 io94nb4f9 164 io94pb4f9 165 io95nb4f9 160 io95pb4f9 161 io97nb4f9 158 io97pb4f9 159 io99nb4f9 154 io99pb4f9 155 io100nb4f9 146 io100pb4f9 147 io101nb4f9 152 io101pb4f9 153 io103nb4f9/clken 142 io103pb4f9/clkep 143 io104nb4f9/clkfn 136 io104pb4f9/clkfp 137 bank 5 io105nb5f10/clkgn 128 io105pb5f10/clkgp 129 io106nb5f10/clkhn 122 io106pb5f10/clkhp 123 io107nb5f10 118 io107pb5f10 119 io114nb5f11 112 io114pb5f11 113 io115nb5f11 110 io115pb5f11 111 io116nb5f11 106 io116pb5f11 107 io117nb5f11 104 io117pb5f11 105 io119nb5f11 100 cq352 AX500 function pin number io119pb5f11 101 io121nb5f11 98 io121pb5f11 99 io123nb5f11 94 io123pb5f11 95 io125nb5f11 92 io125pb5f11 93 bank 6 io126pb6f12 86 io127nb6f12 84 io127pb6f12 85 io129nb6f12 82 io129pb6f12 83 io131nb6f12 78 io131pb6f12 79 io133nb6f12 76 io133pb6f12 77 io134nb6f12 72 io134pb6f12 73 io135nb6f12 70 io135pb6f12 71 io137nb6f13 66 io137pb6f13 67 io138nb6f13 64 io138pb6f13 65 io139nb6f13 60 io139pb6f13 61 io141nb6f13 54 io141pb6f13 55 io142nb6f13 58 io142pb6f13 59 io143nb6f13 52 io143pb6f13 53 io145nb6f13 48 io145pb6f13 49 cq352 AX500 function pin number io146nb6f13 46 io146pb6f13 47 bank 7 io147nb7f14 40 io147pb7f14 41 io148nb7f14 42 io148pb7f14 43 io149nb7f14 36 io149pb7f14 37 io151nb7f14 30 io151pb7f14 31 io152nb7f14 34 io152pb7f14 35 io153nb7f14 28 io153pb7f14 29 io155nb7f14 24 io155pb7f14 25 io157nb7f14 22 io157pb7f14 23 io159nb7f15 16 io159pb7f15 17 io160nb7f15 18 io160pb7f15 19 io161nb7f15 12 io161pb7f15 13 io163nb7f15 10 io163pb7f15 11 io165nb7f15 6 io165pb7f15 7 io167nb7f15 4 io167pb7f15 5 dedicated i/o gnd 1 gnd 9 gnd 15 cq352 AX500 function pin number
axcelerator family fpgas revision 18 3-105 gnd 21 gnd 27 gnd 33 gnd 39 gnd 45 gnd 51 gnd 57 gnd 63 gnd 69 gnd 75 gnd 81 gnd 88 gnd 89 gnd 97 gnd 103 gnd 109 gnd 115 gnd 121 gnd 133 gnd 145 gnd 151 gnd 157 gnd 163 gnd 169 gnd 176 gnd 177 gnd 186 gnd 192 gnd 198 gnd 204 gnd 210 gnd 216 gnd 222 gnd 228 gnd 234 cq352 AX500 function pin number gnd 240 gnd 246 gnd 252 gnd 258 gnd 264 gnd 265 gnd 274 gnd 280 gnd 286 gnd 292 gnd 298 gnd 310 gnd 322 gnd 330 gnd 334 gnd 340 gnd 345 gnd/lp 352 nc 91 nc 117 nc 130 nc 131 nc 148 nc 174 nc 268 nc 294 nc 307 nc 308 nc 327 nc 328 pra 312 prb 311 prc 135 prd 134 tck 349 cq352 AX500 function pin number tdi 348 tdo 347 tms 350 trst 351 vcca 3 vcca 14 vcca 32 vcca 56 vcca 74 vcca 87 vcca 102 vcca 114 vcca 150 vcca 162 vcca 175 vcca 191 vcca 209 vcca 233 vcca 251 vcca 263 vcca 279 vcca 291 vcca 329 vcca 339 vccda 2 vccda 44 vccda 90 vccda 116 vccda 132 vccda 149 vccda 178 vccda 221 vccda 266 vccda 293 vccda 309 cq352 AX500 function pin number
package pin assignments 3-106 revision 18 vccda 346 vccib0 321 vccib0 333 vccib0 344 vccib1 273 vccib1 285 vccib1 297 vccib2 227 vccib2 239 vccib2 245 vccib2 257 vccib3 185 vccib3 197 vccib3 203 vccib3 215 vccib4 144 vccib4 156 vccib4 168 vccib5 96 vccib5 108 vccib5 120 vccib6 50 vccib6 62 vccib6 68 vccib6 80 vccib7 8 vccib7 20 vccib7 26 vccib7 38 vccpla 317 vccplb 315 vccplc 303 vccpld 301 vccple 140 vccplf 138 cq352 AX500 function pin number vccplg 126 vccplh 124 vcompla 318 vcomplb 316 vcomplc 304 vcompld 302 vcomple 141 vcomplf 139 vcomplg 127 vcomplh 125 vpump 267 cq352 AX500 function pin number
axcelerator family fpgas revision 18 3-107 cq352 ax1000 function pin number bank 0 io02nb0f0 341 io02pb0f0 342 io03pb0f0 343 io04nb0f0 337 io04pb0f0 338 io08nb0f0 331 io08pb0f0 332 io09nb0f0 335 io09pb0f0 336 io24nb0f2 325 io24pb0f2 326 io25nb0f2 323 io25pb0f2 324 io30nb0f2/hclkan 319 io30pb0f2/hclkap 320 io31nb0f2/hclkbn 313 io31pb0f2/hclkbp 314 bank 1 io32nb1f3/hclkcn 305 io32pb1f3/hclkcp 306 io33nb1f3/hclkdn 299 io33pb1f3/hclkdp 300 io38nb1f3 295 io38pb1f3 296 io54nb1f5 287 io54pb1f5 288 io55nb1f5 289 io55pb1f5 290 io56nb1f5 281 io56pb1f5 282 io57nb1f5 283 io57pb1f5 284 io59nb1f5 277 io59pb1f5 278 io60nb1f5 275 io60pb1f5 276 io61nb1f5 271 io61pb1f5 272 io63nb1f5 269 io63pb1f5 270 bank 2 io64nb2f6 259 io64pb2f6 260 io67nb2f6 261 io67pb2f6 262 io68nb2f6 255 io68pb2f6 256 io69nb2f6 253 io69pb2f6 254 io74nb2f7 249 io74pb2f7 250 io75nb2f7 247 io75pb2f7 248 io76nb2f7 243 io76pb2f7 244 io77nb2f7 241 io77pb2f7 242 io78nb2f7 237 io78pb2f7 238 io79nb2f7 235 io79pb2f7 236 io82nb2f7 231 io82pb2f7 232 io83nb2f7 229 io83pb2f7 230 io94nb2f8 225 io94pb2f8 226 io95nb2f8 223 io95pb2f8 224 cq352 ax1000 function pin number bank 3 io96nb3f9 217 io96pb3f9 218 io97nb3f9 219 io97pb3f9 220 io99nb3f9 213 io99pb3f9 214 io108nb3f10 211 io108pb3f10 212 io109nb3f10 207 io109pb3f10 208 io111nb3f10 205 io111pb3f10 206 io112nb3f10 199 io112pb3f10 200 io113nb3f10 201 io113pb3f10 202 io115nb3f10 195 io115pb3f10 196 io116nb3f10 193 io116pb3f10 194 io117nb3f10 189 io117pb3f10 190 io124nb3f11 183 io124pb3f11 184 io125nb3f11 187 io125pb3f11 188 io127nb3f11 181 io127pb3f11 182 io128nb3f11 179 io128pb3f11 180 bank 4 io130nb4f12 172 io130pb4f12 173 io131nb4f12 170 cq352 ax1000 function pin number
package pin assignments 3-108 revision 18 io131pb4f12 171 io132nb4f12 166 io132pb4f12 167 io133nb4f12 164 io133pb4f12 165 io134nb4f12 160 io134pb4f12 161 io136nb4f12 158 io136pb4f12 159 io137nb4f12 154 io137pb4f12 155 io138nb4f12 152 io138pb4f12 153 io153nb4f14 146 io153pb4f14 147 io159nb4f14/clken 142 io159pb4f14/clkep 143 io160nb4f14/clkfn 136 io160pb4f14/clkfp 137 bank 5 io161nb5f15/clkgn 128 io161pb5f15/clkgp 129 io162nb5f15/clkhn 122 io162pb5f15/clkhp 123 io167nb5f15 118 io167pb5f15 119 io183nb5f17 110 io183pb5f17 111 io184nb5f17 112 io184pb5f17 113 io185nb5f17 104 io185pb5f17 105 io186nb5f17 106 io186pb5f17 107 io187nb5f17 98 cq352 ax1000 function pin number io187pb5f17 99 io188nb5f17 100 io188pb5f17 101 io190nb5f17 94 io190pb5f17 95 io192nb5f17 92 io192pb5f17 93 bank 6 io193pb6f18 86 io194nb6f18 84 io194pb6f18 85 io196nb6f18 78 io196pb6f18 79 io197nb6f18 82 io197pb6f18 83 io198nb6f18 76 io198pb6f18 77 io203nb6f19 72 io203pb6f19 73 io204nb6f19 70 io204pb6f19 71 io205nb6f19 66 io205pb6f19 67 io206nb6f19 64 io206pb6f19 65 io207nb6f19 60 io207pb6f19 61 io208nb6f19 58 io208pb6f19 59 io211nb6f19 54 io211pb6f19 55 io212nb6f19 52 io212pb6f19 53 io223nb6f20 48 io223pb6f20 49 cq352 ax1000 function pin number io224nb6f20 46 io224pb6f20 47 bank 7 io225nb7f21 40 io225pb7f21 41 io226nb7f21 42 io226pb7f21 43 io237nb7f22 34 io237pb7f22 35 io238nb7f22 36 io238pb7f22 37 io240nb7f22 30 io240pb7f22 31 io241nb7f22 28 io241pb7f22 29 io242nb7f22 24 io242pb7f22 25 io244nb7f22 22 io244pb7f22 23 io245nb7f22 18 io245pb7f22 19 io246nb7f22 16 io246pb7f22 17 io249nb7f23 12 io249pb7f23 13 io250nb7f23 10 io250pb7f23 11 io256nb7f23 4 io256pb7f23 5 io257nb7f23 6 io257pb7f23 7 dedicated i/o gnd 1 gnd 9 gnd 15 cq352 ax1000 function pin number
axcelerator family fpgas revision 18 3-109 gnd 21 gnd 27 gnd 33 gnd 39 gnd 45 gnd 51 gnd 57 gnd 63 gnd 69 gnd 75 gnd 81 gnd 88 gnd 89 gnd 97 gnd 103 gnd 109 gnd 115 gnd 121 gnd 133 gnd 145 gnd 151 gnd 157 gnd 163 gnd 169 gnd 176 gnd 177 gnd 186 gnd 192 gnd 198 gnd 204 gnd 210 gnd 216 gnd 222 gnd 228 gnd 234 cq352 ax1000 function pin number gnd 240 gnd 246 gnd 252 gnd 258 gnd 264 gnd 265 gnd 274 gnd 280 gnd 286 gnd 292 gnd 298 gnd 310 gnd 322 gnd 330 gnd 334 gnd 340 gnd 345 gnd 352 nc 91 nc 130 nc 131 nc 174 nc 268 nc 307 nc 308 pra 312 prb 311 prc 135 prd 134 tck 349 tdi 348 tdo 347 tms 350 trst 351 vcca 3 cq352 ax1000 function pin number vcca 14 vcca 32 vcca 56 vcca 74 vcca 87 vcca 102 vcca 114 vcca 150 vcca 162 vcca 175 vcca 191 vcca 209 vcca 233 vcca 251 vcca 263 vcca 279 vcca 291 vcca 329 vcca 339 vccda 2 vccda 44 vccda 90 vccda 116 vccda 117 vccda 132 vccda 148 vccda 149 vccda 178 vccda 221 vccda 266 vccda 293 vccda 294 vccda 309 vccda 327 vccda 328 cq352 ax1000 function pin number
package pin assignments 3-110 revision 18 vccda 346 vccib0 321 vccib0 333 vccib0 344 vccib1 273 vccib1 285 vccib1 297 vccib2 227 vccib2 239 vccib2 245 vccib2 257 vccib3 185 vccib3 197 vccib3 203 vccib3 215 vccib4 144 vccib4 156 vccib4 168 vccib5 96 vccib5 108 vccib5 120 vccib6 50 vccib6 62 vccib6 68 vccib6 80 vccib7 8 vccib7 20 vccib7 26 vccib7 38 vccpla 317 vccplb 315 vccplc 303 vccpld 301 vccple 140 vccplf 138 cq352 ax1000 function pin number vccplg 126 vccplh 124 vcompla 318 vcomplb 316 vcomplc 304 vcompld 302 vcomple 141 vcomplf 139 vcomplg 127 vcomplh 125 vpump 267 cq352 ax1000 function pin number
axcelerator family fpgas revision 18 3-111 cq352 ax2000 function pin number bank 0 io01nb0f0 341 io01pb0f0 342 io02pb0f0 343 io04nb0f0 337 io04pb0f0 338 io05nb0f0 335 io05pb0f0 336 io08nb0f0 331 io08pb0f0 332 io37nb0f3 325 io37pb0f3 326 io38nb0f3 323 io38pb0f3 324 io41nb0f3/hclkan 319 io41pb0f3/hclkap 320 io42nb0f3/hclkbn 313 io42pb0f3/hclkbp 314 bank 1 io43nb1f4/hclkcn 305 io43pb1f4/hclkcp 306 io44nb1f4/hclkdn 299 io44pb1f4/hclkdp 300 io48nb1f4 295 io48pb1f4 296 io65nb1f6 283 io65pb1f6 284 io66nb1f6 289 io66pb1f6 290 io68nb1f6 287 io68pb1f6 288 io69nb1f6 275 io69pb1f6 276 io70nb1f6 281 io70pb1f6 282 io71nb1f6 277 io71pb1f6 278 io73nb1f6 269 io73pb1f6 270 io74nb1f6 271 io74pb1f6 272 bank 2 io87nb2f8 261 io87pb2f8 262 io88nb2f8 255 io88pb2f8 256 io89nb2f8 259 io89pb2f8 260 io91nb2f8 253 io91pb2f8 254 io99nb2f9 249 io99pb2f9 250 io100nb2f9 247 io100pb2f9 248 io107nb2f10 243 io107pb2f10 244 io110nb2f10 241 io110pb2f10 242 io111nb2f10 237 io111pb2f10 238 io112nb2f10 235 io112pb2f10 236 io113nb2f10 231 io113pb2f10 232 io114nb2f10 229 io114pb2f10 230 io115nb2f10 225 io115pb2f10 226 io117nb2f10 223 io117pb2f10 224 cq352 ax2000 function pin number bank 3 io129nb3f12 219 io129pb3f12 220 io132nb3f12 217 io132pb3f12 218 io137nb3f12 213 io137pb3f12 214 io139nb3f13 211 io139pb3f13 212 io141nb3f13 205 io141pb3f13 206 io142nb3f13 207 io142pb3f13 208 io145nb3f13 199 io145pb3f13 200 io146nb3f13 201 io146pb3f13 202 io147nb3f13 193 io147pb3f13 194 io148nb3f13 195 io148pb3f13 196 io149nb3f13 189 io149pb3f13 190 io161nb3f15 183 io161pb3f15 184 io163nb3f15 187 io163pb3f15 188 io165nb3f15 181 io165pb3f15 182 io167nb3f15 179 io167pb3f15 180 bank 4 io181nb4f17 172 io181pb4f17 173 io182nb4f17 170 cq352 ax2000 function pin number
package pin assignments 3-112 revision 18 io182pb4f17 171 io183nb4f17 166 io183pb4f17 167 io184nb4f17 164 io184pb4f17 165 io185nb4f17 160 io185pb4f17 161 io190nb4f17 158 io190pb4f17 159 io191nb4f17 154 io191pb4f17 155 io192nb4f17 152 io192pb4f17 153 io207nb4f19 146 io207pb4f19 147 io212nb4f19/clken 142 io212pb4f19/clkep 143 io213nb4f19/clkfn 136 io213pb4f19/clkfp 137 bank 5 io214nb5f20/clkgn 128 io214pb5f20/clkgp 129 io215nb5f20/clkhn 122 io215pb5f20/clkhp 123 io217nb5f20 118 io217pb5f20 119 io236nb5f22 110 io236pb5f22 111 io237nb5f22 112 io237pb5f22 113 io238nb5f22 104 io238pb5f22 105 io239nb5f22 106 io239pb5f22 107 io240nb5f22 100 cq352 ax2000 function pin number io240pb5f22 101 io242nb5f22 94 io242pb5f22 95 io243nb5f22 98 io243pb5f22 99 io244nb5f22 92 io244pb5f22 93 bank 6 io257pb6f24 86 io258nb6f24 84 io258pb6f24 85 io261nb6f24 82 io261pb6f24 83 io262nb6f24 78 io262pb6f24 79 io265nb6f24 76 io265pb6f24 77 io279nb6f26 72 io279pb6f26 73 io280nb6f26 70 io280pb6f26 71 io281nb6f26 66 io281pb6f26 67 io282nb6f26 64 io282pb6f26 65 io284nb6f26 60 io284pb6f26 61 io285nb6f26 58 io285pb6f26 59 io286nb6f26 54 io286pb6f26 55 io287nb6f26 52 io287pb6f26 53 io294nb6f27 48 io294pb6f27 49 cq352 ax2000 function pin number io296nb6f27 46 io296pb6f27 47 bank 7 io300nb7f28 42 io300pb7f28 43 io303nb7f28 40 io303pb7f28 41 io310nb7f29 34 io310pb7f29 35 io311nb7f29 36 io311pb7f29 37 io312nb7f29 28 io312pb7f29 29 io315nb7f29 30 io315pb7f29 31 io316nb7f29 22 io316pb7f29 23 io317nb7f29 24 io317pb7f29 25 io318nb7f29 18 io318pb7f29 19 io320nb7f29 16 io320pb7f29 17 io334nb7f31 10 io334pb7f31 11 io335nb7f31 12 io335pb7f31 13 io338nb7f31 6 io338pb7f31 7 io341nb7f31 4 io341pb7f31 5 dedicated i/o gnd 1 gnd 9 gnd 15 cq352 ax2000 function pin number
axcelerator family fpgas revision 18 3-113 gnd 21 gnd 27 gnd 33 gnd 39 gnd 45 gnd 51 gnd 57 gnd 63 gnd 69 gnd 75 gnd 81 gnd 88 gnd 89 gnd 97 gnd 103 gnd 109 gnd 115 gnd 121 gnd 133 gnd 145 gnd 151 gnd 157 gnd 163 gnd 169 gnd 176 gnd 177 gnd 186 gnd 192 gnd 198 gnd 204 gnd 210 gnd 216 gnd 222 gnd 228 gnd 234 cq352 ax2000 function pin number gnd 240 gnd 246 gnd 252 gnd 258 gnd 264 gnd 265 gnd 274 gnd 280 gnd 286 gnd 292 gnd 298 gnd 310 gnd 322 gnd 330 gnd 334 gnd 340 gnd 345 gnd 352 pra 312 prb 311 prc 135 prd 134 tck 349 tdi 348 tdo 347 tms 350 trst 351 vcca 3 vcca 14 vcca 32 vcca 56 vcca 74 vcca 87 vcca 102 vcca 114 cq352 ax2000 function pin number vcca 150 vcca 162 vcca 175 vcca 191 vcca 209 vcca 233 vcca 251 vcca 263 vcca 279 vcca 291 vcca 329 vcca 339 vccda 2 vccda 44 vccda 90 vccda 91 vccda 116 vccda 117 vccda 130 vccda 131 vccda 132 vccda 148 vccda 149 vccda 174 vccda 178 vccda 221 vccda 266 vccda 268 vccda 293 vccda 294 vccda 307 vccda 308 vccda 309 vccda 327 vccda 328 cq352 ax2000 function pin number
package pin assignments 3-114 revision 18 vccda 346 vccib0 321 vccib0 333 vccib0 344 vccib1 273 vccib1 285 vccib1 297 vccib2 227 vccib2 239 vccib2 245 vccib2 257 vccib3 185 vccib3 197 vccib3 203 vccib3 215 vccib4 144 vccib4 156 vccib4 168 vccib5 96 vccib5 108 vccib5 120 vccib6 50 vccib6 62 vccib6 68 vccib6 80 vccib7 8 vccib7 20 vccib7 26 vccib7 38 vccpla 317 vccplb 315 vccplc 303 vccpld 301 vccple 140 vccplf 138 cq352 ax2000 function pin number vccplg 126 vccplh 124 vcompla 318 vcomplb 316 vcomplc 304 vcompld 302 vcomple 141 vcomplf 139 vcomplg 127 vcomplh 125 vpump 267 cq352 ax2000 function pin number
axcelerator family fpgas revision 18 3-115 cg624 note for package manufacturing and environmental information, visit resource center at http://www.microsemi.com/soc/pr oducts/rescenter/package/index.html . 1 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae 2 3 4 5 6 7 8 9 10 11 12 14 13 15 16 17 18 19 20 21 22 23 24 25
package pin assignments 3-116 revision 18 cg624 ax1000 function pin number bank 0 io00nb0f0 f8 io00pb0f0 f7 io02nb0f0 g7 io02pb0f0 g6 io04nb0f0 e9 io04pb0f0 d8 io06nb0f0 g9 io06pb0f0 g8 io07pb0f0 b6 io08nb0f0 f10 io08pb0f0 f9 io09pb0f0 c7 io10nb0f0 h8 io10pb0f0 h7 io11nb0f0 d10 io11pb0f0 d9 io12nb0f1 b5 io12pb0f1 b4 io13nb0f1 a7 io13pb0f1 a6 io14nb0f1 c9 io14pb0f1 c8 io15pb0f1 b7 io16nb0f1 a5 io16pb0f1 a4 io17nb0f1 a9 io17pb0f1 b9 io18nb0f1 d12 io18pb0f1 d11 io20nb0f1 b11 io20pb0f1 b10 io21nb0f1 a11 io21pb0f1 a10 io22nb0f2 h10 io22pb0f2 h9 io23nb0f2 e11 io23pb0f2 f11 io24nb0f2 d7 io24pb0f2 e7 io25pb0f2 b12 io26nb0f2 h11 io26pb0f2 g11 io27nb0f2 c11 io27pb0f2 b8 io28nb0f2 j13 io28pb0f2 k13 io29nb0f2 j8 io29pb0f2 j7 io30nb0f2/hclkan g13 io30pb0f2/hclkap g12 io31nb0f2/hclkbn c13 io31pb0f2/hclkbp c12 bank 1 io32nb1f3/hclkcn g15 io32pb1f3/hclkcp g14 io33nb1f3/hclkdn b14 io33pb1f3/hclkdp b13 io34nb1f3 g16 io34pb1f3 h16 io35nb1f3 c17 io35pb1f3 b18 io36nb1f3 h18 io36pb1f3 h15 io37nb1f3 h13 io38nb1f3 e15 io38pb1f3 f15 io39nb1f3 d14 io39pb1f3 c14 io40nb1f3 d16 io40pb1f3 d15 io41nb1f4 f16 cg624 ax1000 function pin number io42nb1f4 g21 io42pb1f4 g20 io43nb1f4 a16 io43pb1f4 a15 io44nb1f4 a20 io44pb1f4 a19 io45nb1f4 b17 io45pb1f4 b16 io46nb1f4 g17 io46pb1f4 h17 io47nb1f4 a17 io48nb1f4 c19 io48pb1f4 c18 io49nb1f4 b20 io49pb1f4 b19 io50nb1f4 h20 io50pb1f4 h19 io51nb1f4 a22 io51pb1f4 a21 io52nb1f4 c21 io52pb1f4 c20 io53nb1f4 b22 io53pb1f4 b21 io54nb1f5 j18 io54pb1f5 j19 io55nb1f5 d18 io55pb1f5 d17 io56nb1f5 f20 io56pb1f5 f19 io58nb1f5 e17 io58pb1f5 f17 io60nb1f5 d20 io60pb1f5 d19 io62nb1f5 e18 io62pb1f5 f18 io63nb1f5 g19 cg624 ax1000 function pin number
axcelerator family fpgas revision 18 3-117 io63pb1f5 g18 bank 2 io64nb2f6 m17 io64pb2f6 g22 io65nb2f6 j21 io65pb2f6 j20 io66nb2f6 l23 io66pb2f6 k20 io67nb2f6 f23 io67pb2f6 e23 io68nb2f6 l18 io68pb2f6 k18 io70nb2f6 e24 io70pb2f6 d24 io71nb2f6 h23 io71pb2f6 g23 io72nb2f6 l19 io72pb2f6 k19 io74nb2f7 j22 io74pb2f7 h22 io75nb2f7 n23 io75pb2f7 m23 io76nb2f7 n17 io76pb2f7 n16 io77nb2f7 l22 io77pb2f7 k22 io78nb2f7 m19 io78pb2f7 m18 io79nb2f7 n19 io79pb2f7 n18 io80nb2f7 l21 io80pb2f7 l20 io82nb2f7 p18 io82pb2f7 p17 io83nb2f7 n22 io83pb2f7 m22 cg624 ax1000 function pin number io84nb2f7 m20 io84pb2f7 m21 io86nb2f8 e25 io86pb2f8 d25 io87nb2f8 l24 io87pb2f8 k24 io88nb2f8 g24 io88pb2f8 f24 io89nb2f8 j25 io90nb2f8 g25 io90pb2f8 f25 io91nb2f8 l25 io91pb2f8 k25 io92nb2f8 j24 io92pb2f8 h24 io93pb2f8 j23 io94nb2f8 n24 io94pb2f8 m24 io95nb2f8 n25 io95pb2f8 m25 bank 3 io96nb3f9 t18 io96pb3f9 r18 io97nb3f9 n20 io97pb3f9 p24 io98nb3f9 p20 io98pb3f9 p19 io99nb3f9 p21 io100nb3f9 t22 io100pb3f9 w24 io101nb3f9 r22 io101pb3f9 p22 io102nb3f9 u19 io102pb3f9 t19 io104nb3f9 v20 io104pb3f9 u20 cg624 ax1000 function pin number io105nb3f9 r23 io105pb3f9 p23 io106nb3f9 r19 io106pb3f9 r20 io107nb3f10 ab24 io108nb3f10 r25 io108pb3f10 p25 io109nb3f10 u25 io109pb3f10 t25 io110nb3f10 u24 io110pb3f10 u23 io112nb3f10 t24 io112pb3f10 r24 io113nb3f10 y25 io113pb3f10 w25 io114nb3f10 v23 io114pb3f10 v24 io116nb3f10 aa24 io116pb3f10 y24 io117nb3f10 ab25 io117pb3f10 aa25 io118nb3f11 t20 io118pb3f11 r21 io120nb3f11 w22 io120pb3f11 w23 io122nb3f11 v22 io122pb3f11 u22 io124nb3f11 y23 io124pb3f11 aa23 io126nb3f11 v21 io126pb3f11 u21 io128nb3f11 y22 io128pb3f11 y21 bank 4 io129nb4f12 w20 io129pb4f12 y20 cg624 ax1000 function pin number
package pin assignments 3-118 revision 18 io131nb4f12 v19 io131pb4f12 w19 io133nb4f12 y18 io133pb4f12 y19 io135nb4f12 w18 io135pb4f12 v18 io137nb4f12 y17 io137pb4f12 aa17 io138nb4f12 ab19 io138pb4f12 ab18 io139nb4f13 aa19 io139pb4f13 u18 io140nb4f13 ac20 io140pb4f13 ac21 io141nb4f13 ad17 io141pb4f13 ad18 io142nb4f13 ad21 io142pb4f13 ad22 io143nb4f13 ab17 io143pb4f13 ac17 io144pb4f13 ae22 io145nb4f13 ae15 io145pb4f13 ae16 io146nb4f13 ad19 io146pb4f13 ad20 io147nb4f13 ad15 io147pb4f13 ad16 io148pb4f13 ae21 io149nb4f13 ad14 io149pb4f13 ac14 io150nb4f13 ae19 io150pb4f13 ae20 io151nb4f13 v17 io151pb4f13 w17 io152nb4f14 ab16 io152pb4f14 w16 cg624 ax1000 function pin number io153nb4f14 y15 io153pb4f14 y16 io155nb4f14 v15 io155pb4f14 v16 io156nb4f14 ab14 io156pb4f14 ab15 io157nb4f14 ae14 io157pb4f14 ac18 io158nb4f14 ac15 io158pb4f14 ac19 io159nb4f14/clken w14 io159pb4f14/clkep w15 io160nb4f14/clkfn ac13 io160pb4f14/clkfp ad13 bank 5 io161nb5f15/clkgn w13 io161pb5f15/clkgp y13 io162nb5f15/clkhn ac12 io162pb5f15/clkhp ad12 io163nb5f15 v9 io163pb5f15 v10 io164nb5f15 v11 io164pb5f15 t13 io165nb5f15 u13 io165pb5f15 v13 io167nb5f15 w11 io167pb5f15 w12 io168nb5f15 ab6 io168pb5f15 aa6 io169nb5f15 v8 io169pb5f15 v7 io171nb5f16 w8 io171pb5f16 w9 io172nb5f16 ab8 io172pb5f16 ac8 io173nb5f16 aa11 cg624 ax1000 function pin number io173pb5f16 y11 io174nb5f16 ab10 io174pb5f16 ab11 io175nb5f16 ac9 io175pb5f16 ae9 io177nb5f16 aa8 io177pb5f16 y8 io178nb5f16 y6 io178pb5f16 w6 io179nb5f16 y10 io179pb5f16 w10 io180nb5f16 y7 io180pb5f16 w7 io181nb5f17 ad9 io181pb5f17 ad10 io182nb5f17 ae10 io182pb5f17 ae11 io183nb5f17 ad7 io183pb5f17 ad8 io184nb5f17 ab9 io185nb5f17 ae6 io185pb5f17 ae7 io186nb5f17 ae4 io186pb5f17 ae5 io187nb5f17 aa9 io187pb5f17 y9 io188nb5f17 u8 io189nb5f17 ad5 io189pb5f17 ad6 io191nb5f17 ac5 io191pb5f17 ac6 io192nb5f17 ab7 io192pb5f17 ac7 bank 6 io193nb6f18 u6 io193pb6f18 u5 cg624 ax1000 function pin number
axcelerator family fpgas revision 18 3-119 io194nb6f18 y3 io194pb6f18 aa3 io195nb6f18 v6 io195pb6f18 w4 io197nb6f18 r5 io197pb6f18 u3 io198nb6f18 p6 io199nb6f18 y5 io199pb6f18 w5 io200nb6f18 v3 io200pb6f18 w3 io201nb6f18 t7 io201pb6f18 u7 io202nb6f18 v2 io203nb6f19 w2 io203pb6f19 y2 io204nb6f19 aa1 io204pb6f19 ab1 io205nb6f19 r6 io205pb6f19 t6 io206nb6f19 w1 io206pb6f19 y1 io207nb6f19 t2 io207pb6f19 u2 io208nb6f19 t1 io208pb6f19 u1 io209nb6f19 aa2 io209pb6f19 ab2 io210nb6f19 p5 io211nb6f19 m1 io211pb6f19 n1 io212nb6f19 p1 io212pb6f19 r1 io213nb6f19 r8 io213pb6f19 t8 io215nb6f20 u4 cg624 ax1000 function pin number io215pb6f20 v4 io216nb6f20 p8 io216pb6f20 r3 io217nb6f20 p7 io217pb6f20 r7 io219nb6f20 r4 io219pb6f20 t4 io220nb6f20 p2 io220pb6f20 r2 io221nb6f20 n4 io221pb6f20 p4 io223nb6f20 m2 io223pb6f20 n2 io224nb6f20 n3 io224pb6f20 p3 bank 7 io225nb7f21 j2 io225pb7f21 j1 io226pb7f21 g2 io227nb7f21 h3 io227pb7f21 h2 io229nb7f21 k2 io229pb7f21 l2 io230nb7f21 k1 io230pb7f21 l1 io231nb7f21 e2 io231pb7f21 f2 io232nb7f21 f1 io232pb7f21 g1 io233nb7f21 l3 io233pb7f21 m3 io234nb7f21 d1 io234pb7f21 e1 io235nb7f21 k4 io235pb7f21 l4 io236nb7f22 m6 cg624 ax1000 function pin number io237nb7f22 n8 io237pb7f22 n7 io238nb7f22 m5 io239nb7f22 l6 io239pb7f22 l5 io240nb7f22 m4 io241nb7f22 l7 io241pb7f22 m7 io242nb7f22 j3 io243nb7f22 m9 io243pb7f22 m8 io244nb7f22 p9 io244pb7f22 n6 io245nb7f22 k8 io245pb7f22 l8 io246nb7f22 f3 io246pb7f22 e3 io247nb7f23 k7 io247pb7f23 k6 io248nb7f23 d2 io249nb7f23 g4 io249pb7f23 g3 io251nb7f23 n10 io251pb7f23 n9 io253nb7f23 h4 io253pb7f23 j4 io255nb7f23 j6 io255pb7f23 j5 io257nb7f23 h5 io257pb7f23 h6 dedicated i/o gnd k5 gnd a18 gnd a2 gnd a24 gnd a25 cg624 ax1000 function pin number
package pin assignments 3-120 revision 18 gnd a8 gnd aa10 gnd aa16 gnd aa18 gnd aa21 gnd aa5 gnd ab22 gnd ab4 gnd ac10 gnd ac16 gnd ac23 gnd ac3 gnd ad1 gnd ad2 gnd ad24 gnd ad25 gnd ae1 gnd ae18 gnd ae2 gnd ae24 gnd ae25 gnd ae8 gnd b1 gnd b2 gnd b24 gnd b25 gnd c10 gnd c16 gnd c23 gnd c3 gnd d22 gnd d4 gnd e10 gnd e16 gnd e21 gnd e5 cg624 ax1000 function pin number gnd/lp e8 gnd h1 gnd h21 gnd h25 gnd k21 gnd k23 gnd k3 gnd l11 gnd l12 gnd l13 gnd l14 gnd l15 gnd m11 gnd m12 gnd m13 gnd m14 gnd m15 gnd n11 gnd n12 gnd n13 gnd n14 gnd n15 gnd p11 gnd p12 gnd p13 gnd p14 gnd p15 gnd r11 gnd r12 gnd r13 gnd r14 gnd r15 gnd t21 gnd t23 gnd t3 gnd t5 cg624 ax1000 function pin number gnd v1 gnd v25 gnd v5 nc a14 nc aa20 nc ab13 nc ad4 nc ae12 nc f21 nc g10 pra f13 prb a13 prc ab12 prd ae13 tck f5 tdi c5 tdo f6 tms d6 trst e6 vcca ab20 vcca f22 vcca f4 vcca j17 vcca j9 vcca k10 vcca k11 vcca k15 vcca k16 vcca l10 vcca l16 vcca r10 vcca r16 vcca t10 vcca t11 vcca t15 vcca t16 cg624 ax1000 function pin number
axcelerator family fpgas revision 18 3-121 vcca u17 vcca u9 vcca y4 vccda a12 vccda aa13 vccda aa15 vccda aa7 vccda ac11 vccda ad11 vccda ae17 vccda b15 vccda c15 vccda c6 vccda d13 vccda e13 vccda e19 vccda g5 vccda n21 vccda n5 vccda w21 vccib0 a3 vccib0 b3 vccib0 c4 vccib0 d5 vccib0 j10 vccib0 j11 vccib0 k12 vccib1 a23 vccib1 b23 vccib1 c22 vccib1 d21 vccib1 j15 vccib1 j16 vccib1 k14 vccib2 c24 vccib2 c25 cg624 ax1000 function pin number vccib2 d23 vccib2 e22 vccib2 k17 vccib2 l17 vccib2 m16 vccib3 aa22 vccib3 ab23 vccib3 ac24 vccib3 ac25 vccib3 p16 vccib3 r17 vccib3 t17 vccib4 ab21 vccib4 ac22 vccib4 ad23 vccib4 ae23 vccib4 t14 vccib4 u15 vccib4 u16 vccib5 ab5 vccib5 ac4 vccib5 ad3 vccib5 ae3 vccib5 t12 vccib5 u10 vccib5 u11 vccib6 aa4 vccib6 ab3 vccib6 ac1 vccib6 ac2 vccib6 p10 vccib6 r9 vccib6 t9 vccib7 c1 vccib7 c2 vccib7 d3 cg624 ax1000 function pin number vccib7 e4 vccib7 k9 vccib7 l9 vccib7 m10 vccpla e12 vccplb j12 vccplc e14 vccpld h14 vccple y14 vccplf u14 vccplg y12 vccplh u12 vcompla f12 vcomplb h12 vcomplc f14 vcompld j14 vcomple aa14 vcomplf v14 vcomplg aa12 vcomplh v12 vpump e20 cg624 ax1000 function pin number
package pin assignments 3-122 revision 18 cg624 ax2000 function pin number bank 0 io00nb0f0 d7* io00pb0f0 e7* io01nb0f0 g7 io01pb0f0 g6 io02nb0f0 b5 io02pb0f0 b4 io04pb0f0 c7 io05nb0f0 f8 io05pb0f0 f7 io06nb0f0 h8 io06pb0f0 h7 io11nb0f0 j8 io11pb0f0 j7 io12pb0f1 b6 io13nb0f1 e9* io13pb0f1 d8* io15nb0f1 c9 io15pb0f1 c8 io16nb0f1 a5 io16pb0f1 a4 io17nb0f1 d10 io17pb0f1 d9 io18nb0f1 a7 io18pb0f1 a6 io19nb0f1 g9 io19pb0f1 g8 io20pb0f1 b7 io23nb0f2 f10 io23pb0f2 f9 io26nb0f2 c11* io26pb0f2 b8* note: *not routed on the same package layer and to adjacent lga pads as its differential pair complement. recommended to be used as a single-ended i/o. io27nb0f2 h10 io27pb0f2 h9 io28nb0f2 a9 io28pb0f2 b9 io30nb0f2 b11 io30pb0f2 b10 io31nb0f2 e11 io31pb0f2 f11 io33nb0f2 d12 io33pb0f2 d11 io34nb0f3 a11 io34pb0f3 a10 io37nb0f3 j13 io37pb0f3 k13 io38nb0f3 h11 io38pb0f3 g11 io40pb0f3 b12 io41nb0f3/hclkan g13 io41pb0f3/hclkap g12 io42nb0f3/hclkbn c13 io42pb0f3/hclkbp c12 bank 1 io43nb1f4/hclkcn g15 io43pb1f4/hclkcp g14 io44nb1f4/hclkdn b14 io44pb1f4/hclkdp b13 io45nb1f4 h13 io47nb1f4 d14 io47pb1f4 c14 io48nb1f4 a16 io48pb1f4 a15 io49pb1f4 h15 cg624 ax2000 function pin number note: *not routed on the same package layer and to adjacent lga pads as its differential pair complement. recommended to be used as a single-ended i/o. io51nb1f4 e15 io51pb1f4 f15 io52nb1f4 a17 io55nb1f5 g16 io55pb1f5 h16 io56nb1f5 a20 io56pb1f5 a19 io57nb1f5 d16 io57pb1f5 d15 io58nb1f5 a22 io58pb1f5 a21 io59nb1f5 f16 io61nb1f5 g17 io61pb1f5 h17 io62nb1f5 b17 io62pb1f5 b16 io63nb1f5 h18 io65nb1f6 c17 io66pb1f6 b18 io67nb1f6 j18 io67pb1f6 j19 io68nb1f6 b20 io68pb1f6 b19 io69nb1f6 e17 io69pb1f6 f17 io70nb1f6 b22 io70pb1f6 b21 io71pb1f6 g18 io73nb1f6 g19 io74nb1f6 c19 io74pb1f6 c18 io75nb1f6 d18 cg624 ax2000 function pin number note: *not routed on the same package layer and to adjacent lga pads as its differential pair complement. recommended to be used as a single-ended i/o.
axcelerator family fpgas revision 18 3-123 io75pb1f6 d17 io76nb1f7 c21 io76pb1f7 c20 io79nb1f7 h20 io79pb1f7 h19 io80nb1f7 e18 io80pb1f7 f18 io81nb1f7 g21 io81pb1f7 g20 io82nb1f7 f20 io82pb1f7 f19 io85nb1f7 d20* io85pb1f7 d19* bank 2 io86nb2f8 f23 io86pb2f8 e23 io87nb2f8 h23 io87pb2f8 g23 io88nb2f8 e24 io88pb2f8 d24 io89nb2f8 m17* io89pb2f8 g22* io91nb2f8 j22 io91pb2f8 h22 io92nb2f8 l18 io92pb2f8 k18 io96nb2f9 g24 io96pb2f9 f24 io97nb2f9 j21 io97pb2f9 j20 io98pb2f9 j23 io99nb2f9 l19 cg624 ax2000 function pin number note: *not routed on the same package layer and to adjacent lga pads as its differential pair complement. recommended to be used as a single-ended i/o. io99pb2f9 k19 io100nb2f9 e25 io100pb2f9 d25 io103pb2f9 k20 io105nb2f9 m19 io105pb2f9 m18 io106nb2f9 j24 io106pb2f9 h24 io107nb2f10 l23* io107pb2f10 n16* io109nb2f10 l22 io109pb2f10 k22 io110nb2f10 g25 io110pb2f10 f25 io111nb2f10 l21 io111pb2f10 l20 io112nb2f10 l24 io112pb2f10 k24 io113nb2f10 n17 io115nb2f10 m20 io115pb2f10 m21 io117nb2f10 n19 io117pb2f10 n18 io118nb2f11 j25 io121nb2f11 n24 io121pb2f11 m24 io122nb2f11 l25 io122pb2f11 k25 io123nb2f11 n22 io123pb2f11 m22 io124nb2f11 n23 io124pb2f11 m23 cg624 ax2000 function pin number note: *not routed on the same package layer and to adjacent lga pads as its differential pair complement. recommended to be used as a single-ended i/o. io127nb2f11 p18 io127pb2f11 p17 io128nb2f11 n25 io128pb2f11 m25 bank 3 io129nb3f12 n20 io130pb3f12 p24 io131nb3f12 p21 io133nb3f12 p20 io133pb3f12 p19 io138nb3f12 r23 io138pb3f12 p23 io139nb3f13 r22 io139pb3f13 p22 io141nb3f13 r19 io142nb3f13 r25 io142pb3f13 p25 io143pb3f13 r21 io145nb3f13 t18 io145pb3f13 r18 io146nb3f13 t24 io146pb3f13 r24 io147nb3f13 t20 io147pb3f13 r20 io148nb3f13 u25 io148pb3f13 t25 io149nb3f13 t22 io153nb3f14 u19 io153pb3f14 t19 io154nb3f14 y25 io154pb3f14 w25 io157nb3f14 v20 cg624 ax2000 function pin number note: *not routed on the same package layer and to adjacent lga pads as its differential pair complement. recommended to be used as a single-ended i/o.
package pin assignments 3-124 revision 18 io157pb3f14 u20 io158nb3f14 ab25 io158pb3f14 aa25 io160pb3f14 w24 io161nb3f15 u24 io161pb3f15 u23 io162nb3f15 aa24 io162pb3f15 y24 io163nb3f15 v22 io163pb3f15 u22 io164nb3f15 v23 io164pb3f15 v24 io166nb3f15 ab24 io167nb3f15 v21 io167pb3f15 u21 io168nb3f15 y23 io168pb3f15 aa23 io169nb3f15 w22* io169pb3f15 w23* io170nb3f15 y22 io170pb3f15 y21 bank 4 io171nb4f16 ac20* io171pb4f16 ac21* io172nb4f16 w20 io172pb4f16 y20 io173nb4f16 ad21 io173pb4f16 ad22 io174nb4f16 aa19 io176nb4f16 y18 io176pb4f16 y19 io177nb4f16 ab19 cg624 ax2000 function pin number note: *not routed on the same package layer and to adjacent lga pads as its differential pair complement. recommended to be used as a single-ended i/o. io177pb4f16 ab18 io182nb4f17 v19 io182pb4f17 w19 io183pb4f17 ac19 io184nb4f17 ab17 io184pb4f17 ac17 io185nb4f17 ad19 io185pb4f17 ad20 io187pb4f17 ac18 io188nb4f17 y17 io188pb4f17 aa17 io189pb4f17 ae22 io191nb4f17 w18 io191pb4f17 v18 io192pb4f17 u18 io195pb4f18 ae21 io196nb4f18 ab16 io197nb4f18 ad17 io197pb4f18 ad18 io198nb4f18 v17 io198pb4f18 w17 io199nb4f18 ae19 io199pb4f18 ae20 io200nb4f18 ac15 io201nb4f18 ad15 io201pb4f18 ad16 io202nb4f18 y15 io202pb4f18 y16 io206nb4f19 ab14 io206pb4f19 ab15 io207nb4f19 ae15 io207pb4f19 ae16 cg624 ax2000 function pin number note: *not routed on the same package layer and to adjacent lga pads as its differential pair complement. recommended to be used as a single-ended i/o. io208pb4f19 w16 io209nb4f19 ae14 io210nb4f19 v15 io210pb4f19 v16 io211nb4f19 ad14 io211pb4f19 ac14 io212nb4f19/clken w14 io212pb4f19/clkep w15 io213nb4f19/clkfn ac13 io213pb4f19/clkfp ad13 bank 5 io214nb5f20/clkgn w13 io214pb5f20/clkgp y13 io215nb5f20/clkhn ac12 io215pb5f20/clkhp ad12 io216nb5f20 u13 io216pb5f20 v13 io217nb5f20 ae10 io217pb5f20 ae11 io218nb5f20 w11 io218pb5f20 w12 io222nb5f20 aa11 io222pb5f20 y11 io223pb5f21 ae9 io225nb5f21 ae6 io225pb5f21 ae7 io226nb5f21 y10 io226pb5f21 w10 io227pb5f21 t13 io228nb5f21 ab10 io228pb5f21 ab11 io229nb5f21 ad9 cg624 ax2000 function pin number note: *not routed on the same package layer and to adjacent lga pads as its differential pair complement. recommended to be used as a single-ended i/o.
axcelerator family fpgas revision 18 3-125 io229pb5f21 ad10 io230nb5f21 v11 io233nb5f21 ad7 io233pb5f21 ad8 io234nb5f21 v9 io234pb5f21 v10 io236nb5f22 ac9 io238nb5f22 w8 io238pb5f22 w9 io239nb5f22 ae4 io239pb5f22 ae5 io240nb5f22 ab9 io242nb5f22 aa9 io242pb5f22 y9 io243nb5f22 ad5 io243pb5f22 ad6 io244nb5f22 u8 io246nb5f23 ab8 io246pb5f23 ac8 io247nb5f23 ab7 io247pb5f23 ac7 io250nb5f23 aa8 io250pb5f23 y8 io251nb5f23 v8 io251pb5f23 v7 io252nb5f23 y7 io252pb5f23 w7 io253nb5f23 ac5 io253pb5f23 ac6 io254nb5f23 y6 io254pb5f23 w6 io256nb5f23 ab6* cg624 ax2000 function pin number note: *not routed on the same package layer and to adjacent lga pads as its differential pair complement. recommended to be used as a single-ended i/o. io256pb5f23 aa6* bank 6 io257nb6f24 y3 io257pb6f24 aa3 io258nb6f24 v3 io258pb6f24 w3 io259nb6f24 aa2 io259pb6f24 ab2 io260nb6f24 v6* io260pb6f24 w4* io262nb6f24 u4 io262pb6f24 v4 io263nb6f24 y5 io263pb6f24 w5 io268nb6f25 u6 io268pb6f25 u5 io269pb6f25 u3 io272nb6f25 t2 io272pb6f25 u2 io273nb6f25 w2 io273pb6f25 y2 io274nb6f25 r6 io274pb6f25 t6 io275nb6f25 t7 io275pb6f25 u7 io277nb6f25 v2 io278nb6f26 r4 io278pb6f26 t4 io279pb6f26 r3 io280nb6f26 r5 io281nb6f26 aa1 io281pb6f26 ab1 cg624 ax2000 function pin number note: *not routed on the same package layer and to adjacent lga pads as its differential pair complement. recommended to be used as a single-ended i/o. io284nb6f26 r8 io284pb6f26 t8 io285nb6f26 w1 io285pb6f26 y1 io286nb6f26 p2 io286pb6f26 r2 io287nb6f26 t1 io287pb6f26 u1 io288nb6f26 p5 io290nb6f27 p6 io291nb6f27 p1 io291pb6f27 r1 io292nb6f27 p7 io292pb6f27 r7 io293nb6f27 m1 io293pb6f27 n1 io294nb6f27 p8 io296nb6f27 n3 io296pb6f27 p3 io298nb6f27 n4 io298pb6f27 p4 io299nb6f27 m2 io299pb6f27 n2 bank 7 io300nb7f28 p9* io300pb7f28 n6* io302nb7f28 m6 io304nb7f28 n8 io304pb7f28 n7 io308nb7f28 m4 io309nb7f28 l3 io309pb7f28 m3 cg624 ax2000 function pin number note: *not routed on the same package layer and to adjacent lga pads as its differential pair complement. recommended to be used as a single-ended i/o.
package pin assignments 3-126 revision 18 io310nb7f29 n10 io310pb7f29 n9 io311nb7f29 k1 io311pb7f29 l1 io313nb7f29 m5 io316nb7f29 l6 io316pb7f29 l5 io317nb7f29 k2 io317pb7f29 l2 io318nb7f29 k4 io318pb7f29 l4 io320nb7f29 j3 io321nb7f30 j2 io321pb7f30 j1 io323nb7f30 l7 io323pb7f30 m7 io324nb7f30 m9 io324pb7f30 m8 io327nb7f30 f1 io327pb7f30 g1 io328nb7f30 k7 io328pb7f30 k6 io329nb7f30 d1 io329pb7f30 e1 io331pb7f30 g2 io332nb7f31 h3 io332pb7f31 h2 io333nb7f31 e2 io333pb7f31 f2 io334nb7f31 h4 io334pb7f31 j4 io335nb7f31 h5 cg624 ax2000 function pin number note: *not routed on the same package layer and to adjacent lga pads as its differential pair complement. recommended to be used as a single-ended i/o. io335pb7f31 h6 io337nb7f31 d2 io338nb7f31 j6 io338pb7f31 j5 io339nb7f31 f3 io339pb7f31 e3 io340nb7f31 g4* io340pb7f31 g3* io341nb7f31 k8 io341pb7f31 l8 dedicated i/o gnd k5 gnd a18 gnd a2 gnd a24 gnd a25 gnd a8 gnd aa10 gnd aa16 gnd aa18 gnd aa21 gnd aa5 gnd ab22 gnd ab4 gnd ac10 gnd ac16 gnd ac23 gnd ac3 gnd ad1 gnd ad2 gnd ad24 gnd ad25 cg624 ax2000 function pin number note: *not routed on the same package layer and to adjacent lga pads as its differential pair complement. recommended to be used as a single-ended i/o. gnd ae1 gnd ae18 gnd ae2 gnd ae24 gnd ae25 gnd ae8 gnd b1 gnd b2 gnd b24 gnd b25 gnd c10 gnd c16 gnd c23 gnd c3 gnd d22 gnd d4 gnd e10 gnd e16 gnd e21 gnd e5 gnd e8 gnd h1 gnd h21 gnd h25 gnd k21 gnd k23 gnd k3 gnd l11 gnd l12 gnd l13 gnd l14 gnd l15 cg624 ax2000 function pin number note: *not routed on the same package layer and to adjacent lga pads as its differential pair complement. recommended to be used as a single-ended i/o.
axcelerator family fpgas revision 18 3-127 gnd m11 gnd m12 gnd m13 gnd m14 gnd m15 gnd n11 gnd n12 gnd n13 gnd n14 gnd n15 gnd p11 gnd p12 gnd p13 gnd p14 gnd p15 gnd r11 gnd r12 gnd r13 gnd r14 gnd r15 gnd t21 gnd t23 gnd t3 gnd t5 gnd v1 gnd v25 gnd v5 pra f13 prb a13 prc ab12 prd ae13 tck f5 cg624 ax2000 function pin number note: *not routed on the same package layer and to adjacent lga pads as its differential pair complement. recommended to be used as a single-ended i/o. tdi c5 tdo f6 tms d6 trst e6 vcca ab20 vcca f22 vcca f4 vcca j17 vcca j9 vcca k10 vcca k11 vcca k15 vcca k16 vcca l10 vcca l16 vcca r10 vcca r16 vcca t10 vcca t11 vcca t15 vcca t16 vcca u17 vcca u9 vcca y4 vccda a12 vccda a14 vccda aa13 vccda aa15 vccda aa20 vccda aa7 vccda ab13 vccda ac11 cg624 ax2000 function pin number note: *not routed on the same package layer and to adjacent lga pads as its differential pair complement. recommended to be used as a single-ended i/o. vccda ad11 vccda ad4 vccda ae12 vccda ae17 vccda b15 vccda c15 vccda c6 vccda d13 vccda e13 vccda e19 vccda f21 vccda g10 vccda g5 vccda n21 vccda n5 vccda w21 vccib0 a3 vccib0 b3 vccib0 c4 vccib0 d5 vccib0 j10 vccib0 j11 vccib0 k12 vccib1 a23 vccib1 b23 vccib1 c22 vccib1 d21 vccib1 j15 vccib1 j16 vccib1 k14 vccib2 c24 vccib2 c25 cg624 ax2000 function pin number note: *not routed on the same package layer and to adjacent lga pads as its differential pair complement. recommended to be used as a single-ended i/o.
package pin assignments 3-128 revision 18 vccib2 d23 vccib2 e22 vccib2 k17 vccib2 l17 vccib2 m16 vccib3 aa22 vccib3 ab23 vccib3 ac24 vccib3 ac25 vccib3 p16 vccib3 r17 vccib3 t17 vccib4 ab21 vccib4 ac22 vccib4 ad23 vccib4 ae23 vccib4 t14 vccib4 u15 vccib4 u16 vccib5 ab5 vccib5 ac4 vccib5 ad3 vccib5 ae3 vccib5 t12 vccib5 u10 vccib5 u11 vccib6 aa4 vccib6 ab3 vccib6 ac1 vccib6 ac2 vccib6 p10 vccib6 r9 cg624 ax2000 function pin number note: *not routed on the same package layer and to adjacent lga pads as its differential pair complement. recommended to be used as a single-ended i/o. vccib6 t9 vccib7 c1 vccib7 c2 vccib7 d3 vccib7 e4 vccib7 k9 vccib7 l9 vccib7 m10 vccpla e12 vccplb j12 vccplc e14 vccpld h14 vccple y14 vccplf u14 vccplg y12 vccplh u12 vcompla f12 vcomplb h12 vcomplc f14 vcompld j14 vcomple aa14 vcomplf v14 vcomplg aa12 vcomplh v12 vpump e20 cg624 ax2000 function pin number note: *not routed on the same package layer and to adjacent lga pads as its differential pair complement. recommended to be used as a single-ended i/o.
revision 18 4-1 4 ? datasheet information list of changes the following table lists critical changes that were made in the current version of the document. revision changes page revision 18 (march 2012) table 2-1 ? absolute maximum ratings was updated to correct the maximum dc core supply voltage (vcca) from 1.6 v to 1.7 v (sar 36786). the maximum input voltage (vi) was corrected from 3.75 v to 4.1 v (sar 35419). 2-1 values for tristate leakage current ioz, and iih and iil were added to ta b l e 2 - 3 ? standby current (sars 35774, 32021). 2-2 figure 2-2 ? vccplx and vcomplx power supply connect was updated to correct the units for the resistance from "w" to (sar 36415). 2-9 in the introduction to the "user i/os" section , the following sentence was added to clarify the slew rate setting (sar 34943): the slew rate setting is effective for both rising and falling edges. 2-11 figure 2-3 ? use of an external resistor for 5 v tolerance was revised to show the vcci and gnd clamp diodes. the explanatory text above the figure was revised as well (sar 34942). 2-13 eq 3 for 5 v tolerance was corrected to change vdiode from 0.6 v to 0.7 v (sar 36786). 2-13 additional information was added to the "using the weak pull-up and pull-down circuits" section to clarify how the weak pull-up and pull-down resistors are physically implemented (sar 34945). 2-17 the description for the c inclk parameter in table 2-18 ? input capacitance was changed from "input capacitance on clock pin" to "input capacitance on hclk and rclk pin" (sar 34944). 2-21 table 2-19 ? i/o input rise time and fall time* is new (sar 34942). 2-21 the minimum vil for 1.5 v lvcmos and pci was corrected from ?0.5 to ?0.3 in table 2-29 ? dc input and output levels and table 2-33 ? dc input and output levels (sar 34358). 2-38 , 2-40 support for simulati ng the gclr/ gpset feature in the axcelerator family was added in libero software v9.0 spi1. reference to the section explaining this in the antifuse macro library guide was added to the "r-cell" section (sar 26413). 2-58 the enable signal in figure 2-32 ? r-cell delays was corrected to show it is active low rather than active high (sar 34946). 2-59 revision 17 (september 2011) the versioning system for datasheets has been changed. datasheets are assigned a revision number that increments each time the datasheet is revised. the "axcelerator family device status" table indicates the status for each device in the device family. iii the "features" section , "programmable interconnect element" section , and "security" section were revised to clarify that although no existing security measures can give an absolute guar antee, microsemi fpgas implement the best security available in the industry (sar 32865). i , 1-1 , 2-108
datasheet information 4-2 revision 18 revision 17 (continued) the c180 package was removed from product tables and the "package pin assignments" section ( pdn 0909 ). 3-1 package names used in the "axcelerator family product profile" and "package pin assignments" section were revised to matc h standards given in package mechanical drawings (sar 27395). i , 3-1 the "introduction" section for "user i/os" was updated as follows: "the user does not need to assign vref pins for outbuf and tribuf. vref pins are needed only for input and bidirectional i/os" (sars 24181, 24309). 2-11 power values in table 2-4 ? default cload/vcci were updated to reflect those of smartpower (sar 33945). 2-3 two parameter names were corrected in figure 2-10 ? output buffer delays . one occurrence of t enlz was changed to t enzl and one occurrence of t enhz was changed to t enzh (sar 33890). 2-22 the "timing model" section was updated with new timing values. timing tables in the "i/o specifications" section were updated to include enable paths. values in the timing tables in the "voltage-referenced i/o standards" section and "differential standards" section were updated. table 2-63 ? r-cell was updated (sar 33945). 2-8 , 2-26 to 2-53 figure 2-11 ? timing model was replaced (sar 33043). 2-23 the timing tables for "ram" and "fifo" were updated (sar 33945). 2-90 to 2-106 "data registers (drs)" values were modified for idcode and usercode (sars 18257, 26406). 2-108 the package diagram for the "cq208" package was incorrect and has been replaced with the correct di agram (sars 23865, 26345). 3-89 revision 16 (v2.8, oct. 2009) the datasheet was updated to include ax2000-cq2526 information. n/a mil-std-883 class b is no longer supported by axcelerator fpgas and as a result was removed. n/a a footnote was added to the "introduction" in the "axcelerator clock management system" section. 2-75 revision 15 (v2.7, nov. 2008) rohs-compliant information was added to the "ordering information" . ii actgen was changed to smartgen because actgen is obsolete. n/a revision 14 (v2.6) in ta b l e 2 - 4 , the units for the p load , p 10 , and p i/o were updated from mw/mhz to mw/mhz. 2-3 in the "pin descriptions" section, the hclk and clk descriptions were updated to include tie-off information. 2-9 the "global resource distribution" section was updated. 2-70 the " cg624" table was updated. 3-116 revision 13 (v2.5) a note was added to ta b l e 2 - 2 . 2-1 in the "package thermal characteristics" , the temperature was changed from 150c to 125c. 2-6 revision changes page
axcelerator family fpgas revision 18 4-3 revision 12 (v2.4) revised ordering information and timing da ta to reflect phase out of ?3 speed grade options. table 2-3 was updated. 2 revision 11 (v2.3) the "packaging data" section is new. iv table 2-2 was updated. 2-1 "vccda supply voltage" was updated. 2-9 "pra/b/c/d probe a, b, c and d" was updated. 2-10 the "user i/os" was updated. 2-11 revision 10 (v2.2) figure 1-3 was updated. 1-2 table 2-2 was updated. 2-1 the "power-up/down sequence" section was updated. 2-1 table 2-4 was updated. 2-3 table 2-5 was updated. 2-4 the "timing characteristics" section was added. 2-7 table 2-7 was updated. 2-7 figure 2-1 was updated. 2-8 the external setup and clock-to-out (pad-to-pad) equations in the "hardwired clock ? using lvttl 24 ma high slew clock i/o" section were updated. 2-8 the external setup and clock-to-out (pad-to-pad) in the "routed clock ? using lvttl 24 ma high slew clock i/o" section were updated. 2-8 the "global pins" section was updated. 2-10 the "user i/os" section was updated. 2-11 table 2-17 was updated. 2-19 figure 2-8 was updated. 2-20 figure 2-13 and figure 2-14 were updated. 2-24 the following timing parameters were renamed in i/o timing characteristic tables from ta b l e 2 - 2 2 to table 2-60 : t ioclkq > t iclkq t ioclky > t oclkq 2-26 to 2-52 timing numbers were updated from ta b l e 2 - 2 2 to table 2-78 . 2-26 to 2-69 the "r-cell" section was updated. 2-58 figure 2-59 was updated. 2-89 figure 2-60 was updated. 2-89 figure 2-67 was updated. 2-100 figure 2-68 was updated. 2-101 table 2-89 to ta b l e 2 - 9 3 were updated. 2-90 to 2-94 table 2-98 to table 2-102 were updated. 2-102 to 2-106 revision changes page
datasheet information 4-4 revision 18 revision 10 (continued) the "trst" section was updated. 2-107 the "global set fuse" section was added. 2-109 a footnote was added to "fg896" for the ax2000 regarding pins ab1, ae2, g1, and k2. 3-52 pinouts for the ax250, AX500, and ax1000 were added for "cq352" . 3-98 pinout for the ax1000 was added for "cg624" . 3-115 revision 9 (v2.1) table 2-79 was updated. 2-69 the "low power mode" section was updated. 2-106 revision 8 (v2.0) table 1 has been updated. i the "ordering information" section has been updated. ii the "device resources" section has been updated. ii the "temperature grade offerings" section is new. iii the "speed grade and temperature grade matrix" section has been updated. iii table 2-9 has been updated. 2-12 table 2-10 has been updated. 2-12 table 2-1 has been updated. 2-1 table 2-2 has been updated. 2-1 table 2-3 has been updated. 2-2 table 2-4 has been updated. 2-3 table 2-5 has been updated. 2-4 the "power estimation example" section has been updated. 2-5 the "thermal characteristics" section has been updated. 2-6 the "package thermal characteristics" section has been updated. 2-6 the "timing characteristics" section has been updated. 2-7 the "pin descriptions" section has been updated. 2-9 timing numbers have been updated from the "3.3 v lvttl" section to the "timing characteristics" section. many ac loads were updated as well. 2-25 to 2-59 timing characteristics for the "hardwired clocks" and "routed clocks" sections were updated. 2-66 , 2-68 table 2-89 to ta b l e 2 - 9 2 and table 2-98 to table 2-99 were updated. 2-90 to 2-93 , 2-102 to 2-103 the following sections were updated: "low power mode" , "interface" , "data registers (drs)" , "security" , "silicon explorer ii probe interface" , and "programming" 2-106 to 2-110 in the "pq208" (AX500) section, pins 2, 52, and 156 changed from v ccda to v cca . for pins 170 and 171, the i/o names refer to pair 23 instead of 24. 3-84 revision changes page
axcelerator family fpgas revision 18 4-5 revision 8 (continued) the following changes were made in the "fg676" (AX500) section: ae2, ae25 change from nc to gnd. af2, af25 changed from gnd to nc ab4, af24, c1, c26 changed from v ccda to v cca ad15 change from v ccda to v comple ad17 changed from v comple to v ccda 3-37 in the "fg896" (ax2000) section, the ak28 changed from vccib5 to vccib4. 3-52 the "cq352" and "cg624" sections are new. 3-98 , 3-115 revision 7 (advance v1.6) all i/o fifo capability was removed. n/a table 1 was updated. i figure 1-9 was updated. 1-7 figure 2-5 was updated. 2-16 the "using an i/o register" section was updated. 2-16 the ax250 and ax1000 descriptions were added to the "fg484" section. 3-21 revision 6 (advance v1.5) table 2-3 was updated. 2-2 figure 2-1 was updated. 2-8 figure 2-48 was updated. 2-75 figure 2-52 was updated. 2-82 revision 5 (advance v1.4) in the "pq208" table, pin 196 was missing, but it has been added in this version with a function of gnd. 3-84 the following pins in the "fg484" table for AX500 were changed: pin g7 is gnd/lp pins ab8, c10, c11, c14, ab16 are nc. 3-21 the "fg676" table was updated. 3-37 revision 4 (advance v1.3) the "device resources" section was updated for the cs180. ii the "programmable interconnect element" and figure 1-2 are new. 1-1 and 1-2 the "cs180" table is new. 3-1 the "pq208" tables for the AX500 were updated. the following pins were not defined in the previous version: gnd 21 io106pb5f10/clkhp 71 gnd 136 3-84 revision 3 (advance v1.2) table 1 , "ordering information" , "device resources" , and the product plan table were updated. i , ii the following figures and tables were updated: figure 1-3 figure 1-8 (new) table 2-3 figure 2-2 table 2-8 figure 2-11 1-2 1-6 2-2 2-9 2-12 2-23 the "design environment" section was updated. 1-7 the "package thermal characteristics" was updated. 2-6 revision changes page
datasheet information 4-6 revision 18 revision 3 (continued) the timing characteristics tables from pages 2-26 to 2-60 were updated. 2-26 to 2-60 the "global resources" section was updated. 2-66 the timing characteristics tables from pages 2-102 to 2-103 were updated. 2-102 to 2-103 the "pq208" , "fg256" , and "fg324" tables are new. 3-9 , 3-16 , 3-84 revision changes page
axcelerator family fpgas revision 18 4-7 datasheet categories categories in order to provide the latest information to des igners, some datasheet parameters are published before data has been fully characterized from silicon devices. the data provided for a given device, as highlighted in the "axcelerator family device status" table on page iii , is designated as either "product brief," "advance," "preliminary," or "production." th e definitions of these categories are as follows: product brief the product brief is a summarized version of a data sheet (advance or producti on) and contains general product information. this document gives an overvi ew of specific device and family information. advance this version contains initial estimated information bas ed on simulation, other products, devices, or speed grades. this information can be used as estimates, bu t not for production. this label only applies to the dc and switching characteristics chapter of the da tasheet and will only be used when the data has not been fully characterized. preliminary the datasheet contains information based on simulation and/or initial characterization. the information is believed to be correct, but changes are possible. production this version contains information that is considered to be final. export administration regulations (ear) the products described in this document are subj ect to the export administ ration regulations (ear). they could require an approved export license prior to export from the united st ates. an export includes release of product or disclosure of technology to a foreign national inside or outside the united states. safety critical, life support, and high-reliability applications policy the products described in this advance status document may not have completed the microsemi qualification process. products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. it is the responsibility of each customer to ensure the fitne ss of any product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. consult the microsemi soc products group terms and conditions for specific liability exclusions relating to life-support applications. a reliability report covering all of the soc products group?s products is available at http://www.microsemi.com/s oc/documents/ort_report.pdf . microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. contact your local sales office for additional reliability information.
5172160-18/3.12 ? 2012 microsemi corporation. all rights reserved. microsemi and the microsemi logo are trademarks of microsemi corporation. all other trademarks and service marks are the property of their respective owners. microsemi corporation (nasdaq: mscc) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security ; enterprise and communications; and industrial and alternative energy markets. products incl ude high-performance, high-reliability analog and rf devices, mixed signal and rf integrated circuits, customizable socs, fpgas, and complete subsystems. microsemi is headquarter ed in aliso viejo, calif. learn more at www.microsemi.com . microsemi corporate headquarters one enterprise, aliso viejo ca 92656 usa within the usa: +1 (949) 380-6100 sales: +1 (949) 380-6136 fax: +1 (949) 215-4996

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